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Commit cbd379b1 authored by Russell King's avatar Russell King
Browse files

Merge branches 'fixes', 'mcpm', 'misc' and 'mmci' into for-next

parents 3e0a07f8 6c93dd43 1b21376a 01259620

Documentation/devicetree/bindings/arm/l2cc.txt

+3 −0
Original line number Diff line number Diff line
@@ -16,6 +16,9 @@ Required properties: 
     performs the same operation).

	"marvell,"aurora-outer-cache: Marvell Controller designed to be

	 compatible with the ARM one with outer cache mode.

	"bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an

	offset needs to be added to the address before passing down to the L2

	cache controller

- cache-unified : Specifies the cache is a unified cache.

- cache-level : Should be set to 2 for a level 2 cache.

- reg : Physical base address and size of cache controller's memory mapped

arch/arm/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -175,6 +175,9 @@ config ARCH_HAS_CPUFREQ 
	  and that the relevant menu configurations are displayed for

	  it.



config ARCH_HAS_BANDGAP

	bool



config GENERIC_HWEIGHT

	bool

	default y

arch/arm/Makefile

+33 −26
Original line number Diff line number Diff line
@@ -59,37 +59,43 @@ comma = , 
# Note that GCC does not numerically define an architecture version

# macro, but instead defines a whole series of macros which makes

# testing for a specific architecture or later rather impossible.

arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)

arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)

arch-$(CONFIG_CPU_32v7)		=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)

arch-$(CONFIG_CPU_32v6)		=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)

# Only override the compiler option if ARMv6. The ARMv6K extensions are

# always available in ARMv7

ifeq ($(CONFIG_CPU_32v6),y)

arch-$(CONFIG_CPU_32v6K)	:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)

arch-$(CONFIG_CPU_32v6K)	=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)

endif

arch-$(CONFIG_CPU_32v5)		:=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)

arch-$(CONFIG_CPU_32v4T)	:=-D__LINUX_ARM_ARCH__=4 -march=armv4t

arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4

arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3

arch-$(CONFIG_CPU_32v5)		=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)

arch-$(CONFIG_CPU_32v4T)	=-D__LINUX_ARM_ARCH__=4 -march=armv4t

arch-$(CONFIG_CPU_32v4)		=-D__LINUX_ARM_ARCH__=4 -march=armv4

arch-$(CONFIG_CPU_32v3)		=-D__LINUX_ARM_ARCH__=3 -march=armv3



# Evaluate arch cc-option calls now

arch-y := $(arch-y)



# This selects how we optimise for the processor.

tune-$(CONFIG_CPU_ARM7TDMI)	:=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM740T)	:=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM9TDMI)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM940T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM946E)	:=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)

tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM925T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_FA526)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110

tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100

tune-$(CONFIG_CPU_XSCALE)	:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_XSC3)		:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_FEROCEON)	:=$(call cc-option,-mtune=marvell-f,-mtune=xscale)

tune-$(CONFIG_CPU_V6)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

tune-$(CONFIG_CPU_V6K)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

tune-$(CONFIG_CPU_ARM7TDMI)	=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM720T)	=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM740T)	=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM9TDMI)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM940T)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM946E)	=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)

tune-$(CONFIG_CPU_ARM920T)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM922T)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM925T)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM926T)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_FA526)	=-mtune=arm9tdmi

tune-$(CONFIG_CPU_SA110)	=-mtune=strongarm110

tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100

tune-$(CONFIG_CPU_XSCALE)	=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_XSC3)		=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_FEROCEON)	=$(call cc-option,-mtune=marvell-f,-mtune=xscale)

tune-$(CONFIG_CPU_V6)		=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

tune-$(CONFIG_CPU_V6K)		=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)



# Evaluate tune cc-option calls now

tune-y := $(tune-y)



ifeq ($(CONFIG_AEABI),y)

CFLAGS_ABI	:=-mabi=aapcs-linux -mno-thumb-interwork
@@ -289,9 +295,10 @@ zImage Image xipImage bootpImage uImage: vmlinux 
zinstall uinstall install: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@



%.dtb: scripts

%.dtb: | scripts

	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@



PHONY += dtbs

dtbs: scripts

	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs

arch/arm/boot/compressed/atags_to_fdt.c

+38 −6
Original line number Diff line number Diff line
@@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path, 
	return fdt_getprop(fdt, offset, property, len);

}



static uint32_t get_cell_size(const void *fdt)

{

	int len;

	uint32_t cell_size = 1;

	const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);



	if (size_len)

		cell_size = fdt32_to_cpu(*size_len);

	return cell_size;

}



static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)

{

	char cmdline[COMMAND_LINE_SIZE];
@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) 
int atags_to_fdt(void *atag_list, void *fdt, int total_space)

{

	struct tag *atag = atag_list;

	uint32_t mem_reg_property[2 * NR_BANKS];

	/* In the case of 64 bits memory size, need to reserve 2 cells for

	 * address and size for each bank */

	uint32_t mem_reg_property[2 * 2 * NR_BANKS];

	int memcount = 0;

	int ret;

	int ret, memsize;



	/* make sure we've got an aligned pointer */

	if ((u32)atag_list & 0x3)
@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) 
				continue;

			if (!atag->u.mem.size)

				continue;

			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);

			mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);

			memsize = get_cell_size(fdt);



			if (memsize == 2) {

				/* if memsize is 2, that means that

				 * each data needs 2 cells of 32 bits,

				 * so the data are 64 bits */

				uint64_t *mem_reg_prop64 =

					(uint64_t *)mem_reg_property;

				mem_reg_prop64[memcount++] =

					cpu_to_fdt64(atag->u.mem.start);

				mem_reg_prop64[memcount++] =

					cpu_to_fdt64(atag->u.mem.size);

			} else {

				mem_reg_property[memcount++] =

					cpu_to_fdt32(atag->u.mem.start);

				mem_reg_property[memcount++] =

					cpu_to_fdt32(atag->u.mem.size);

			}



		} else if (atag->hdr.tag == ATAG_INITRD2) {

			uint32_t initrd_start, initrd_size;

			initrd_start = atag->u.initrd.start;
@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) 
		}

	}



	if (memcount)

		setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);

	if (memcount) {

		setprop(fdt, "/memory", "reg", mem_reg_property,

			4 * memcount * memsize);

	}



	return fdt_pack(fdt);

}

arch/arm/boot/compressed/head.S

+30 −10
Original line number Diff line number Diff line
@@ -142,7 +142,6 @@ start: 
		mov	r7, r1			@ save architecture ID

		mov	r8, r2			@ save atags pointer



#ifndef __ARM_ARCH_2__

		/*

		 * Booting from Angel - need to enter SVC mode and disable

		 * FIQs/IRQs (numeric definitions from angel arm.h source).
@@ -158,10 +157,6 @@ not_angel: 
		safe_svcmode_maskall r0

		msr	spsr_cxsf, r9		@ Save the CPU boot mode in

						@ SPSR

#else

		teqp	pc, #0x0c000003		@ turn off interrupts

#endif



		/*

		 * Note that some cache flushing and other stuff may

		 * be needed here - is there an Angel SWI call for this?
@@ -183,7 +178,19 @@ not_angel: 
		ldr	r4, =zreladdr

#endif



		bl	cache_on

		/*

		 * Set up a page table only if it won't overwrite ourself.

		 * That means r4 < pc && r4 - 16k page directory > &_end.

		 * Given that r4 > &_end is most unfrequent, we add a rough

		 * additional 1MB of room for a possible appended DTB.

		 */

		mov	r0, pc

		cmp	r0, r4

		ldrcc	r0, LC0+32

		addcc	r0, r0, pc

		cmpcc	r4, r0

		orrcc	r4, r4, #1		@ remember we skipped cache_on

		blcs	cache_on



restart:	adr	r0, LC0

		ldmia	r0, {r1, r2, r3, r6, r10, r11, r12}
@@ -229,7 +236,7 @@ restart: adr r0, LC0 
 *   r0  = delta

 *   r2  = BSS start

 *   r3  = BSS end

 *   r4  = final kernel address

 *   r4  = final kernel address (possibly with LSB set)

 *   r5  = appended dtb size (still unknown)

 *   r6  = _edata

 *   r7  = architecture ID
@@ -277,6 +284,7 @@ restart: adr r0, LC0 
		 */

		cmp	r0, #1

		sub	r0, r4, #TEXT_OFFSET

		bic	r0, r0, #1

		add	r0, r0, #0x100

		mov	r1, r6

		sub	r2, sp, r6
@@ -323,12 +331,13 @@ dtb_check_done: 


/*

 * Check to see if we will overwrite ourselves.

 *   r4  = final kernel address

 *   r4  = final kernel address (possibly with LSB set)

 *   r9  = size of decompressed image

 *   r10 = end of this image, including  bss/stack/malloc space if non XIP

 * We basically want:

 *   r4 - 16k page directory >= r10 -> OK

 *   r4 + image length <= address of wont_overwrite -> OK

 * Note: the possible LSB in r4 is harmless here.

 */

		add	r10, r10, #16384

		cmp	r4, r10
@@ -390,7 +399,8 @@ dtb_check_done: 
		add	sp, sp, r6

#endif



		bl	cache_clean_flush

		tst	r4, #1

		bleq	cache_clean_flush



		adr	r0, BSYM(restart)

		add	r0, r0, r6
@@ -402,7 +412,7 @@ wont_overwrite: 
 *   r0  = delta

 *   r2  = BSS start

 *   r3  = BSS end

 *   r4  = kernel execution address

 *   r4  = kernel execution address (possibly with LSB set)

 *   r5  = appended dtb size (0 if not present)

 *   r7  = architecture ID

 *   r8  = atags pointer
@@ -465,6 +475,15 @@ not_relocated: mov r0, #0 
		cmp	r2, r3

		blo	1b



		/*

		 * Did we skip the cache setup earlier?

		 * That is indicated by the LSB in r4.

		 * Do it now if so.

		 */

		tst	r4, #1

		bic	r4, r4, #1

		blne	cache_on



/*

 * The C runtime environment should now be setup sufficiently.

 * Set up some pointers, and start decompressing.
@@ -513,6 +532,7 @@ LC0: .word LC0 @ r1 
		.word	_got_start		@ r11

		.word	_got_end		@ ip

		.word	.L_user_stack_end	@ sp

		.word	_end - restart + 16384 + 1024*1024

		.size	LC0, . - LC0



#ifdef CONFIG_ARCH_RPC