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Commit cabfeaa6 authored by Cooper Jr., Franklin's avatar Cooper Jr., Franklin Committed by Boris Brezillon
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ARM: OMAP2+: Update GPMC and NAND DT binding documentation 



Add additional details to the GPMC NAND documentation to clarify
what is needed to enable NAND DMA prefetch.

Signed-off-by: default avatarFranklin S Cooper Jr <fcooper@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent aa7abd31

Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

+6 −1
Original line number Diff line number Diff line
@@ -46,6 +46,10 @@ Required properties: 
			0 maps to GPMC_WAIT0 pin.

 - gpio-cells:		Must be set to 2



Required properties when using NAND prefetch dma:

 - dmas			GPMC NAND prefetch dma channel

 - dma-names		Must be set to "rxtx"



Timing properties for child nodes. All are optional and default to 0.



 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds
@@ -137,7 +141,8 @@ Example for an AM33xx board: 
		ti,hwmods = "gpmc";

		reg = <0x50000000 0x2000>;

		interrupts = <100>;



		dmas = <&edma 52 0>;

		dma-names = "rxtx";

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ Optional properties: 


		"prefetch-polled"	Prefetch polled mode (default)

		"polled"		Polled mode, without prefetch

		"prefetch-dma"		Prefetch enabled sDMA mode

		"prefetch-dma"		Prefetch enabled DMA mode

		"prefetch-irq"		Prefetch enabled irq mode



 - elm_id:	<deprecated> use "ti,elm-id" instead