Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cab7f8ed authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz
Browse files

ide: remove ->dma_{status,command} fields from ide_hwif_t



* Use ->dma_base + offset instead of ->dma_{status,command}
  and remove no longer needed ->dma_{status,command}.

While at it:

* Use ATA_DMA_* defines.

There should be no functional changes caused by this patch.

Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent ab86f91e
Loading
Loading
Loading
Loading
+21 −21
Original line number Diff line number Diff line
@@ -377,9 +377,10 @@ void ide_dma_host_set(ide_drive_t *drive, int on)
		dma_stat &= ~(1 << (5 + unit));

	if (hwif->host_flags & IDE_HFLAG_MMIO)
		writeb(dma_stat, (void __iomem *)hwif->dma_status);
		writeb(dma_stat,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
	else
		outb(dma_stat, hwif->dma_status);
		outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
}

EXPORT_SYMBOL_GPL(ide_dma_host_set);
@@ -475,18 +476,19 @@ int ide_dma_setup(ide_drive_t *drive)

	/* specify r/w */
	if (mmio)
		writeb(reading, (void __iomem *)hwif->dma_command);
		writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	else
		outb(reading, hwif->dma_command);
		outb(reading, hwif->dma_base + ATA_DMA_CMD);

	/* read DMA status for INTR & ERROR flags */
	dma_stat = hwif->read_sff_dma_status(hwif);

	/* clear INTR & ERROR flags */
	if (mmio)
		writeb(dma_stat | 6, (void __iomem *)hwif->dma_status);
		writeb(dma_stat | 6,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
	else
		outb(dma_stat | 6, hwif->dma_status);
		outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);

	drive->waiting_for_dma = 1;
	return 0;
@@ -512,12 +514,13 @@ void ide_dma_start(ide_drive_t *drive)
	 * we do this part before issuing the drive cmd.
	 */
	if (hwif->host_flags & IDE_HFLAG_MMIO) {
		dma_cmd = readb((void __iomem *)hwif->dma_command);
		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
		/* start DMA */
		writeb(dma_cmd | 1, (void __iomem *)hwif->dma_command);
		writeb(dma_cmd | 1,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	} else {
		dma_cmd = inb(hwif->dma_command);
		outb(dma_cmd | 1, hwif->dma_command);
		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
		outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
	}

	hwif->dma = 1;
@@ -537,12 +540,13 @@ int __ide_dma_end (ide_drive_t *drive)

	if (mmio) {
		/* get DMA command mode */
		dma_cmd = readb((void __iomem *)hwif->dma_command);
		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
		/* stop DMA */
		writeb(dma_cmd & ~1, (void __iomem *)hwif->dma_command);
		writeb(dma_cmd & ~1,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
	} else {
		dma_cmd = inb(hwif->dma_command);
		outb(dma_cmd & ~1, hwif->dma_command);
		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
		outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	}

	/* get DMA status */
@@ -550,9 +554,10 @@ int __ide_dma_end (ide_drive_t *drive)

	if (mmio)
		/* clear the INTR & ERROR bits */
		writeb(dma_stat | 6, (void __iomem *)hwif->dma_status);
		writeb(dma_stat | 6,
		       (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
	else
		outb(dma_stat | 6, hwif->dma_status);
		outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);

	/* purge DMA mappings */
	ide_destroy_dmatable(drive);
@@ -888,11 +893,6 @@ void ide_setup_dma(ide_hwif_t *hwif, unsigned long base)
{
	hwif->dma_base = base;

	if (!hwif->dma_command)
		hwif->dma_command	= hwif->dma_base + 0;
	if (!hwif->dma_status)
		hwif->dma_status	= hwif->dma_base + 2;

	hwif->dma_ops = &sff_dma_ops;
}

+2 −2
Original line number Diff line number Diff line
@@ -106,9 +106,9 @@ void SELECT_MASK(ide_drive_t *drive, int mask)
static u8 ide_read_sff_dma_status(ide_hwif_t *hwif)
{
	if (hwif->host_flags & IDE_HFLAG_MMIO)
		return readb((void __iomem *)hwif->dma_status);
		return readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
	else
		return inb(hwif->dma_status);
		return inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
+6 −6
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ static int cmd648_dma_test_irq(ide_drive_t *drive)
	unsigned long base	= hwif->dma_base - (hwif->channel * 8);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8 mrdmode		= inb(base + 1);

#ifdef DEBUG
@@ -286,7 +286,7 @@ static int cmd64x_dma_test_irq(ide_drive_t *drive)
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  dma_stat		= inb(hwif->dma_status);
	u8  dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
@@ -317,13 +317,13 @@ static int cmd646_1_dma_end(ide_drive_t *drive)

	drive->waiting_for_dma = 0;
	/* get DMA status */
	dma_stat = inb(hwif->dma_status);
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_command);
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_command);
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_status);
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
+5 −5
Original line number Diff line number Diff line
@@ -801,9 +801,9 @@ static void hpt370_irq_timeout(ide_drive_t *drive)
	printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);

	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_command);
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~0x1, hwif->dma_command);
	outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD);
	hpt370_clear_engine(drive);
}

@@ -818,12 +818,12 @@ static void hpt370_dma_start(ide_drive_t *drive)
static int hpt370_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8  dma_stat		= inb(hwif->dma_status);
	u8  dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);

	if (dma_stat & 0x01) {
		/* wait a little */
		udelay(20);
		dma_stat = inb(hwif->dma_status);
		dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
		if (dma_stat & 0x01)
			hpt370_irq_timeout(drive);
	}
@@ -850,7 +850,7 @@ static int hpt374_dma_test_irq(ide_drive_t *drive)
		return 0;
	}

	dma_stat = inb(hwif->dma_status);
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* return 1 if INTR asserted */
	if (dma_stat & 4)
		return 1;
+7 −7
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static u8 superio_ide_inb (unsigned long port)

static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_status);
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
@@ -208,13 +208,13 @@ static int ns87415_dma_end(ide_drive_t *drive)

	drive->waiting_for_dma = 0;
	dma_stat = hwif->read_sff_dma_status(hwif);
	/* get dma command mode */
	dma_cmd = inb(hwif->dma_command);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_command);
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_command);
	outb(dma_cmd | 6, hwif->dma_command);
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
@@ -298,7 +298,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_status);
	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
Loading