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Commit ca4edf65 authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Remove ADRENO_DEVICE_HARD_RESET flag 



Current hang recovery sequence does not try soft reset
for all GMU enabled targets. ADRENO_DEVICE_HARD_RESET
flags is indication to go for hard reset sequence incase
soft reset fails. The latest a6xx_reset() sequence will
not to do any soft reset for GMU enabled targets. Hence
remove the ADRENO_DEVICE_HARD_RESET flag which does
not have any significance.

Change-Id: I44f492545f68d0555780a4c9cb49e24e1e582bc6
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 6b3ddc57

drivers/gpu/msm/adreno.h

+1 −3
Original line number Diff line number Diff line
@@ -555,7 +555,6 @@ struct adreno_device { 
 * attached and enabled

 * @ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED - Set if a CACHE_FLUSH_TS irq storm

 * is in progress

 * @ADRENO_DEVICE_HARD_RESET - Set if soft reset fails and hard reset is needed

 */

enum adreno_device_flags {

	ADRENO_DEVICE_PWRON = 0,
@@ -572,8 +571,7 @@ enum adreno_device_flags { 
	ADRENO_DEVICE_GPMU_INITIALIZED = 11,

	ADRENO_DEVICE_ISDB_ENABLED = 12,

	ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED = 13,

	ADRENO_DEVICE_HARD_RESET = 14,

	ADRENO_DEVICE_CORESIGHT_CX = 16,

	ADRENO_DEVICE_CORESIGHT_CX = 14,

};



/**

drivers/gpu/msm/adreno_a6xx.c

+11 −23
Original line number Diff line number Diff line
@@ -1080,15 +1080,9 @@ static int a6xx_soft_reset(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int reg;



	/*

	 * For the soft reset case with GMU enabled this part is done

	 * by the GMU firmware

	 */

	if (gmu_core_isenabled(device) &&

		!test_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv))

	if (gmu_core_isenabled(device))

		return 0;





	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);

	/*

	 * Do a dummy read to get a brief read cycle delay for the
@@ -1164,9 +1158,6 @@ static int a6xx_reset(struct kgsl_device *device, int fault) 
	/* Transition from ACTIVE to RESET state */

	kgsl_pwrctrl_change_state(device, KGSL_STATE_RESET);



	if (ret) {

		/* If soft reset failed/skipped, then pull the power */

		set_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv);

	/* since device is officially off now clear start bit */

	clear_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv);
@@ -1178,9 +1169,6 @@ static int a6xx_reset(struct kgsl_device *device, int fault) 


		msleep(20);

	}

	}



	clear_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv);



	if (ret)

		return ret;

drivers/gpu/msm/kgsl_gmu.c

+14 −30
Original line number Diff line number Diff line
@@ -1626,8 +1626,6 @@ static int gmu_start(struct kgsl_device *device) 
		break;



	case KGSL_STATE_RESET:

		if (test_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv) ||

			test_bit(GMU_FAULT, &device->gmu_core.flags)) {

		gmu_suspend(device);



		gmu_aop_send_acd_state(device);
@@ -1648,21 +1646,7 @@ static int gmu_start(struct kgsl_device *device) 


		/* Send DCVS level prior to reset*/

		kgsl_pwrctrl_set_default_gpu_pwrlevel(device);

		} else {

			/* GMU fast boot */

			hfi_stop(gmu);



			gmu_aop_send_acd_state(device);



			ret = gmu_dev_ops->rpmh_gpu_pwrctrl(device,

					GMU_FW_START, GMU_COLD_BOOT, 0);

			if (ret)

				goto error_gmu;



			ret = hfi_start(device, gmu, GMU_COLD_BOOT);

			if (ret)

				goto error_gmu;

		}

		break;

	default:

		break;