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Commit c97689d8 authored by Chris Wilson's avatar Chris Wilson
Browse files

agp/intel: Flush the chipset write buffers when changing GTT base 



Flush the chipset write buffers before and after adjusting the GTT base
register, just in case. We only modify this value upon initialisation
(boot and resume) so there should be no outstanding writes, however
there are always those persistent PGTBL_ER that keep getting reported
upon resume.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 55249baa

drivers/char/agp/intel-agp.h

+2 −0
Original line number Diff line number Diff line
@@ -94,6 +94,8 @@ 
#define G4x_GMCH_SIZE_VT_1_5M	(0xa << 8)

#define G4x_GMCH_SIZE_VT_2M	(0xc << 8)



#define GFX_FLSH_CNTL		0x2170 /* 915+ */



#define I810_DRAM_CTL		0x3000

#define I810_DRAM_ROW_0		0x00000001

#define I810_DRAM_ROW_0_SDRAM	0x00000001

drivers/char/agp/intel-gtt.c

+9 −0
Original line number Diff line number Diff line
@@ -814,6 +814,12 @@ static bool intel_enable_gtt(void) 
		}

	}



	/* On the resume path we may be adjusting the PGTBL value, so

	 * be paranoid and flush all chipset write buffers...

	 */

	if (INTEL_GTT_GEN >= 3)

		writel(0, intel_private.registers+GFX_FLSH_CNTL);



	reg = intel_private.registers+I810_PGETBL_CTL;

	writel(intel_private.PGETBL_save, reg);

	if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
@@ -823,6 +829,9 @@ static bool intel_enable_gtt(void) 
		return false;

	}



	if (INTEL_GTT_GEN >= 3)

		writel(0, intel_private.registers+GFX_FLSH_CNTL);



	return true;

}