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Commit c92a90a5 authored by Russell King's avatar Russell King
Browse files

Merge branches 'fixes' and 'misc' into for-next

parents 6d805949 11ce4b33

Documentation/devicetree/bindings/arm/l2c2x0.txt

+3 −0
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@@ -90,6 +90,9 @@ Optional properties: 
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),

  <1> (forcibly enable), property absent (OS specific behavior,

  preferably retain firmware settings)

- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)

- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero

  write (PL310)



Example:

arch/arm/Kconfig

+1 −0
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@@ -27,6 +27,7 @@ config ARM 
	select GENERIC_ALLOCATOR

	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

	select GENERIC_CPU_AUTOPROBE

	select GENERIC_EARLY_IOREMAP

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IRQ_PROBE

arch/arm/boot/dts/r7s72100.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ 
			compatible = "arm,cortex-a9";

			reg = <0>;

			clock-frequency = <400000000>;

			next-level-cache = <&L2>;

		};

	};
@@ -368,6 +369,16 @@ 
			<0xe8202000 0x1000>;

	};



	L2: cache-controller@3ffff000 {

		compatible = "arm,pl310-cache";

		reg = <0x3ffff000 0x1000>;

		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		arm,early-bresp-disable;

		arm,full-line-zero-disable;

		cache-unified;

		cache-level = <2>;

	};



	i2c0: i2c@fcfee000 {

		#address-cells = <1>;

		#size-cells = <0>;

arch/arm/include/asm/cpufeature.h

0 → 100644
+38 −0
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/*

 * Copyright (C) 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __ASM_CPUFEATURE_H

#define __ASM_CPUFEATURE_H



#include <linux/log2.h>

#include <asm/hwcap.h>



/*

 * Due to the fact that ELF_HWCAP is a 32-bit type on ARM, and given the number

 * of optional CPU features it defines, ARM's CPU hardware capability bits have

 * been distributed over separate elf_hwcap and elf_hwcap2 variables, each of

 * which covers a subset of the available CPU features.

 *

 * Currently, only a few of those are suitable for automatic module loading

 * (which is the primary use case of this facility) and those happen to be all

 * covered by HWCAP2. So let's only cover those via the cpu_feature()

 * convenience macro for now (which is used by module_cpu_feature_match()).

 * However, all capabilities are exposed via the modalias, and can be matched

 * using an explicit MODULE_DEVICE_TABLE() that uses __hwcap_feature() directly.

 */

#define MAX_CPU_FEATURES	64

#define __hwcap_feature(x)	ilog2(HWCAP_ ## x)

#define __hwcap2_feature(x)	(32 + ilog2(HWCAP2_ ## x))

#define cpu_feature(x)		__hwcap2_feature(x)



static inline bool cpu_have_feature(unsigned int num)

{

	return num < 32 ? elf_hwcap & BIT(num) : elf_hwcap2 & BIT(num - 32);

}



#endif

arch/arm/include/asm/fixmap.h

+1 −1
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@@ -41,7 +41,7 @@ static const enum fixed_addresses __end_of_fixed_addresses = 


#define FIXMAP_PAGE_COMMON	(L_PTE_YOUNG | L_PTE_PRESENT | L_PTE_XN | L_PTE_DIRTY)



#define FIXMAP_PAGE_NORMAL	(FIXMAP_PAGE_COMMON | L_PTE_MT_WRITEBACK)

#define FIXMAP_PAGE_NORMAL	(pgprot_kernel | L_PTE_XN)

#define FIXMAP_PAGE_RO		(FIXMAP_PAGE_NORMAL | L_PTE_RDONLY)



/* Used by set_fixmap_(io|nocache), both meant for mapping a device */