Merge tag 'nds32-for-linus-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux

* Andestech Internal Vector Interrupt Controller

The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller

suitable for a simpler SoC platform not requiring a more sophisticated and

bigger External Vector Interrupt Controller.

Main node required properties:

- compatible : should at least contain  "andestech,ativic32".

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts

Examples:

	intc: interrupt-controller {

		compatible = "andestech,ativic32";

		#interrupt-cells = <1>;

		interrupt-controller;

	};

Andestech(nds32) AE3XX Platform

-----------------------------------------------------------------------------

The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It

is composed of one Andestech(nds32) processor and AE3XX.

Required properties (in root node):

- compatible = "andestech,ae3xx";

Example:

/dts-v1/;

/ {

	compatible = "andestech,ae3xx";

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&intc>;

};

Andestech(nds32) AG101P Platform

-----------------------------------------------------------------------------

AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)

processors to provide a cost-effective and high performance solution for

majority of embedded systems in variety of application domains. Users may

simply attach their IP on one of the system buses together with certain glue

logics to complete a SoC solution for a specific application. With

comprehensive simulation and design environments, users may evaluate the

system performance of their applications and track bugs of their designs

efficiently. The optional hardware development platform further provides real

system environment for early prototyping and software/hardware co-development.

Required properties (in root node):

	compatible = "andestech,ag101p";

Example:

/dts-v1/;

/ {

	compatible = "andestech,ag101p";

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&intc>;

};

* Andestech L2 cache Controller

The level-2 cache controller plays an important role in reducing memory latency

for high performance systems, such as thoese designs with AndesCore processors.

Level-2 cache controller in general enhances overall system performance

signigicantly and the system power consumption might be reduced as well by

reducing DRAM accesses.

This binding specifies what properties must be available in the device tree

representation of an Andestech L2 cache controller.

Required properties:

	- compatible:

		Usage: required

		Value type: <string>

		Definition: "andestech,atl2c"

	- reg : Physical base address and size of cache controller's memory mapped

	- cache-unified : Specifies the cache is a unified cache.

	- cache-level : Should be set to 2 for a level 2 cache.

* Example

	cache-controller@e0500000 {

		compatible = "andestech,atl2c";

		reg = <0xe0500000 0x1000>;

		cache-unified;

		cache-level = <2>;

	};

* Andestech Processor Binding

This binding specifies what properties must be available in the device tree

representation of a Andestech Processor Core, which is the root node in the

tree.

Required properties:

	- compatible:

		Usage: required

		Value type: <string>

		Definition: Should be "andestech,<core_name>", "andestech,nds32v3" as fallback.

		Must contain "andestech,nds32v3" as the most generic value, in addition to

		one of the following identifiers for a particular CPU core:

		"andestech,n13"

		"andestech,n15"

		"andestech,d15"

		"andestech,n10"

		"andestech,d10"

	- device_type

		Usage: required

		Value type: <string>

		Definition: must be "cpu"

	- reg: Contains CPU index.

	- clock-frequency: Contains the clock frequency for CPU, in Hz.

* Examples

/ {

	cpus {

		cpu@0 {

			device_type = "cpu";

			compatible = "andestech,n13", "andestech,nds32v3";

			reg = <0x0>;

			clock-frequency = <60000000>

		};

	};

};

Andestech ATCPIT100 timer

------------------------------------------------------------------

ATCPIT100 is a generic IP block from Andes Technology, embedded in

Andestech AE3XX platforms and other designs.

This timer is a set of compact multi-function timers, which can be

used as pulse width modulators (PWM) as well as simple timers.

It supports up to 4 PIT channels. Each PIT channel is a

multi-function timer and provide the following usage scenarios:

One 32-bit timer

Two 16-bit timers

Four 8-bit timers

One 16-bit PWM

One 16-bit timer and one 8-bit PWM

Two 8-bit timer and one 8-bit PWM

Required properties:

- compatible	: Should be "andestech,atcpit100"

- reg		: Address and length of the register set

- interrupts	: Reference to the timer interrupt

- clocks 	: a clock to provide the tick rate for "andestech,atcpit100"

- clock-names 	: should be "PCLK" for the peripheral clock source.

Examples:

timer0: timer@f0400000 {

	compatible = "andestech,atcpit100";

	reg = <0xf0400000 0x1000>;

	interrupts = <2>;

	clocks = <&apb>;

	clock-names = "PCLK";

};