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Commit c927d74e authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Marc Zyngier
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dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller 



Add the Device Tree binding documentation for the Microsemi Ocelot
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 33625282

Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt

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Microsemi Ocelot SoC ICPU Interrupt Controller



Required properties:



- compatible : should be "mscc,ocelot-icpu-intr"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- interrupt-parent : phandle of the CPU interrupt controller.

- interrupts : Specifies the CPU interrupt the controller is connected to.



Example:



		intc: interrupt-controller@70000070 {

			compatible = "mscc,ocelot-icpu-intr";

			reg = <0x70000070 0x70>;

			#interrupt-cells = <1>;

			interrupt-controller;

			interrupt-parent = <&cpuintc>;

			interrupts = <2>;

		};