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Commit c8f5d298 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'arc_emac-next'

Caesar Wang says:

====================
arc_emac: fixes the emac issues and cleanup emac drivers

This series patches are based on kernel 4.5-rc7+ version.
Linux version 4.5.0-rc7-next-20160311+ (wxt@nb) (...) #45 SMP Sun Mar 13 16:17:56

The history patch in here:
Patch-v1: https://lkml.org/lkml/2016/3/11/209
Patch-v2: https://lkml.org/lkml/2016/3/13/39

Verified on kylin board with my github.
https://github.com/Caesar-github/rockchip/tree/kylin/next

That's verified on kylin board with ubuntu os.

This series patches are built all pass with Mr.robot on
https://github.com/Caesar-github/linux/tree/build-emac-v3

How to test and verify?

You can refer to the following wiki document.
http://rockchip.wikidot.com/linux-develop-guide

bootup log:
[    1.264740] rockchip_emac 10200000.ethernet: no regulator found
[    1.270908] rockchip_emac 10200000.ethernet: ARC EMAC detected with id: 0x7fd02
[    1.278362] rockchip_emac 10200000.ethernet: IRQ is 29
[    1.283747] rockchip_emac 10200000.ethernet: MAC address is now 06:5d:61:c7:39:41
[    1.291314] rockchip_emac 10200000.ethernet: GPIO lookup for consumer phy-reset
[    1.291333] rockchip_emac 10200000.ethernet: using device tree for GPIO lookup
[    1.663155] rockchip_emac 10200000.ethernet: connected to Generic PHY phy with id 0xffffc816
[    8.863448] rockchip_emac 10200000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

root@localhost:/# busybox ping www.baidu.com
PING www.baidu.com (14.215.177.38): 56 data bytes
64 bytes from 14.215.177.38: seq=0 ttl=48 time=35.046 ms
64 bytes from 14.215.177.38: seq=1 ttl=48 time=35.095 ms
64 bytes from 14.215.177.38: seq=2 ttl=48 time=34.203 ms
64 bytes from 14.215.177.38: seq=3 ttl=48 time=38.516 ms
...
---

1) This series has 6 patches: (1--->9)
net: arc_emac: make the rockchip emac document more compatible
net: arc_emac: add phy reset is optional for device tree
net: arc_emac: support the phy reset for emac driver
net: arc: trivial: cleanup the emac driver
clk: rockchip: add node-id for rk3036 emac hclk
clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
clk: rockchip: add clock-id for rk3036 emac pll source clock
clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
ARM: dts: rockchip: add support emac for RK3036

2) This series patches have the following descriptions:

Hi Rob, David:
PATCH[1/9-2/9]: ====>
net: arc_emac: make the rockchip emac document more compatible
net: arc_emac: add phy reset is optional for device tree

The patches change the rockchip emac document for more compatible and
Add the phy reset property for document.
---

Hi David
PATCH[3/9]: ====>
net: arc_emac: support the phy reset for emac driver

The emac didn't work on kylin board since in some case the clocks parent changed.
The kylin hardware connects the phy reset pin, we should use it with real world.
As the previous patch discuss on https://patchwork.kernel.org/patch/8186801/

And as sergei/Heiko suggestions on
https://patchwork.kernel.org/patch/8564571/
---

Hi David
PATCH[4/9]: ====>
net: arc: trivial: cleanup the emac driver

The first time to look the emac drivers, I think that have to cleanup the drivers with scripts.
Although it's the trivial things, in order to be more read.
---

Hi Heiko,Michael,Stephen:
PATCH[5/9-8/9]: ====> clk: rockchip: rk3036: fix and add node id for emac clock

Four-part from https://patchwork.kernel.org/patch/8564581/
clk: rockchip: add node-id for rk3036 emac hclk
clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
clk: rockchip: add clock-id for rk3036 emac pll source clock
clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036

Add the emac needed clocks for rk3036 SoCs
---

Hi Heiko:
PATCH[9/9]: ====>
ARM: dts: rockchip: add support emac for RK3036

Add the emac needed main info for rk3036 dts.
---

Thanks your reviewing! :)

Changes in v3:
- %s/he/the
- Add the Cc people
- As Sergei comments, the original name is better, so
  %s/reset-gpios/phy-reset-gpios
- Add the Cc people.
- Caused the build error since the missing include head file.
- %s/reset/phy-reset to match the device tree.
- Add the Cc people
- Add the Cc people.
- Add the Cc people.
- Add the Cc people.
- Add the Cc people.
- Add the Cc people.
- rename reset-gpio to phy-reset-gpios.
- change the commit.
- remove the pcfg_output_high, that's really not needed for emac.
- Add the Cc people.
- Fixes the 'zhengxing' to 'Xing Zheng'.

Changes in v2:
- change the commit and remove the repeat the name 'rockchip'.
- %s/phy-reset-gpios/reset-gpios
- As the pervious version, Sergei and Heiko comments on
  https://patchwork.kernel.org/patch/8564571/.
- Nevermind, add signed-off since Heiko the original patch,
  refer the Heiko's test patch on
  https://github.com/mmind/linux-rockchip/commit/a943c588783438ff1c508dfa8c79f1709aa5775e


  :)
- As the robot notice the build error since overflow in implicit
  constant conversion.
- rename phy-reset-gpio to reset-gpios.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 793cf87d af671e7b
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+7 −0
Original line number Diff line number Diff line
@@ -7,6 +7,13 @@ Required properties:
- max-speed: see ethernet.txt file in the same directory.
- phy: see ethernet.txt file in the same directory.

Optional properties:
- phy-reset-gpios : Should specify the gpio for phy reset
- phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
  will have the duration be 1 millisecond.  Numbers greater than 1000 are
  invalid and 1 millisecond will be used instead.

Clock handling:
The clock frequency is needed to calculate and set polling period of EMAC.
It must be provided by one of:
+5 −3
Original line number Diff line number Diff line
* ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs
* ARC EMAC 10/100 Ethernet platform driver for Rockchip RK3036/RK3066/RK3188 SoCs

Required properties:
- compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac"
  according to the target SoC.
- compatible: should be "rockchip,<name>-emac"
   "rockchip,rk3036-emac": found on RK3036 SoCs
   "rockchip,rk3066-emac": found on RK3066 SoCs
   "rockchip,rk3188-emac": found on RK3188 SoCs
- reg: Address and length of the register set for the device
- interrupts: Should contain the EMAC interrupts
- rockchip,grf: phandle to the syscon grf used to control speed and mode
+14 −0
Original line number Diff line number Diff line
@@ -47,6 +47,20 @@
	compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
};

&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
	phy = <&phy0>;
	phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
	phy-reset-duration = <10>; /* millisecond */

	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&i2c1 {
	status = "okay";

+14 −0
Original line number Diff line number Diff line
@@ -60,6 +60,20 @@
	status = "okay";
};

&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
	phy = <&phy0>;
	phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
	phy-reset-duration = <10>; /* millisecond */

	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&emmc {
	status = "okay";
};
+39 −0
Original line number Diff line number Diff line
@@ -186,6 +186,27 @@
		status = "disabled";
	};

	emac: ethernet@10200000 {
		compatible = "rockchip,rk3036-emac", "snps,arc-emac";
		reg = <0x10200000 0x4000>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		rockchip,grf = <&grf>;
		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
		clock-names = "hclk", "macref", "macclk";
		/*
		 * Fix the emac parent clock is DPLL instead of APLL.
		 * since that will cause some unstable things if the cpufreq
		 * is working. (e.g: the accurate 50MHz what mac_ref need)
		 */
		assigned-clocks = <&cru SCLK_MACPLL>;
		assigned-clock-parents = <&cru PLL_DPLL>;
		max-speed = <100>;
		phy-mode = "rmii";
		status = "disabled";
	};

	sdmmc: dwmmc@10214000 {
		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x10214000 0x4000>;
@@ -556,6 +577,24 @@
			};
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
						<2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
						<2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
						<2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
						<2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
						<2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
						<2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
						<2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
						<2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
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