Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c8badda8 authored by Charles Keepax's avatar Charles Keepax Committed by Mark Brown
Browse files

ASoC: arizona: Update handling for input change on an active FLL 



Currently, the driver places no restrictions on changes that can be
applied to an active FLL. However, it is only possible to change the
input for an active FLL, to change the output the FLL should be stopped
and then recofigured. This patch disallows changes in output frequency
and adds some additional handling to ensure the output remains
consistent across an input transition.

Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 5e39a50b

sound/soc/codecs/arizona.c

+19 −0
Original line number Original line Diff line number Diff line
@@ -1500,6 +1500,12 @@ static int arizona_validate_fll(struct arizona_fll *fll, 
{

{

	unsigned int Fvco_min;

	unsigned int Fvco_min;





	if (fll->fout && Fout != fll->fout) {

		arizona_fll_err(fll,

				"Can't change output on active FLL\n");

		return -EINVAL;

	}



	if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {

	if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {

		arizona_fll_err(fll,

		arizona_fll_err(fll,

				"Can't scale %dMHz in to <=13.5MHz\n",

				"Can't scale %dMHz in to <=13.5MHz\n",
@@ -1743,6 +1749,15 @@ static int arizona_enable_fll(struct arizona_fll *fll) 
	if (already_enabled < 0)

	if (already_enabled < 0)

		return already_enabled;

		return already_enabled;





	if (already_enabled) {

		/* Facilitate smooth refclk across the transition */

		regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,

					 ARIZONA_FLL1_GAIN_MASK, 0);

		regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,

					 ARIZONA_FLL1_FREERUN,

					 ARIZONA_FLL1_FREERUN);

	}



	/*

	/*

	 * If we have both REFCLK and SYNCCLK then enable both,

	 * If we have both REFCLK and SYNCCLK then enable both,

	 * otherwise apply the SYNCCLK settings to REFCLK.

	 * otherwise apply the SYNCCLK settings to REFCLK.
@@ -1798,6 +1813,10 @@ static int arizona_enable_fll(struct arizona_fll *fll) 
					 ARIZONA_FLL1_SYNC_ENA,

					 ARIZONA_FLL1_SYNC_ENA,

					 ARIZONA_FLL1_SYNC_ENA);

					 ARIZONA_FLL1_SYNC_ENA);





	if (already_enabled)

		regmap_update_bits_async(arizona->regmap, fll->base + 1,

					 ARIZONA_FLL1_FREERUN, 0);



	ret = wait_for_completion_timeout(&fll->ok,

	ret = wait_for_completion_timeout(&fll->ok,

					  msecs_to_jiffies(250));

					  msecs_to_jiffies(250));

	if (ret == 0)

	if (ret == 0)