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Commit c8a1cecc authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v3.8/cleanup-timer-signed' of...

Merge tag 'omap-for-v3.8/cleanup-timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

Timer clean-up to get us closer to moving timer code to drivers,
and to get rid of CONFIG_OMAP_32K_TIMER and rely on the board
or devicetree provided timer configuration.

Note that these changes are on top of the recent timer fixes.

By Jon Hunter (32) and others
via Tony Lindgren
* tag 'omap-for-v3.8/cleanup-timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

: (71 commits)
  ARM: OMAP3: cm-t3517: use GPTIMER for system clock
  ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
  ARM: OMAP2+: Fix compiler warning for 32k timer
  ARM: OMAP: Remove unnecessary inclusion of dmtimer.h
  ARM: OMAP: Add platform data header for DMTIMERs
  ARM: OMAP: Remove unnecessary omap_dm_timer structure declaration
  ARM: OMAP2+: Remove unnecessary local variable in timer code
  ARM: OMAP: Don't store timers physical address
  ARM: OMAP: Define omap_dm_timer_prepare function as static
  ARM: OMAP: Clean-up dmtimer reset code
  ARM: OMAP: Remove __omap_dm_timer_set_source function
  ARM: OMAP: Remove unnecessary call to clk_get()
  ARM: OMAP: Add dmtimer interrupt disable function
  ARM: OMAP: Fix spurious interrupts when using timer match feature
  ARM: OMAP: Don't restore DMTIMER interrupt status register
  ARM: OMAP: Don't restore of DMTIMER TISTAT register
  ARM: OMAP: Fix dmtimer reset for timer1
  ARM: OMAP2+: Don't use __omap_dm_timer_reset()
  ARM: OMAP2/3: Define HWMOD software reset status for DMTIMERs
  ARM: OMAP3: Correct HWMOD DMTIMER SYSC register declarations
  ...

Change/change conflict in arch/arm/mach-omap2/board-cm-t3517.c.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4c929c8a 26f01998
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OMAP Counter-32K bindings

Required properties:
- compatible:	Must be "ti,omap-counter32k" for OMAP controllers
- reg:		Contains timer register address range (base address and length)
- ti,hwmods:	Name of the hwmod associated to the counter, which is typically
		"counter_32k"

Example:

counter32k: counter@4a304000 {
	compatible = "ti,omap-counter32k";
	reg = <0x4a304000 0x20>;
	ti,hwmods = "counter_32k";
};
+31 −0
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OMAP Timer bindings

Required properties:
- compatible:		Must be "ti,omap2-timer" for OMAP2+ controllers.
- reg:			Contains timer register address range (base address and
			length).
- interrupts: 		Contains the interrupt information for the timer. The
			format is being dependent on which interrupt controller
			the OMAP device uses.
- ti,hwmods:		Name of the hwmod associated to the timer, "timer<X>",
			where <X> is the instance number of the timer from the
			HW spec.

Optional properties:
- ti,timer-alwon:	Indicates the timer is in an alway-on power domain.
- ti,timer-dsp:		Indicates the timer can interrupt the on-chip DSP in
			addition to the ARM CPU.
- ti,timer-pwm: 	Indicates the timer can generate a PWM output.
- ti,timer-secure: 	Indicates the timer is reserved on a secure OMAP device
			and therefore cannot be used by the kernel.

Example:

timer12: timer@48304000 {
	compatible = "ti,omap2-timer";
	reg = <0x48304000 0x400>;
	interrupts = <95>;
	ti,hwmods = "timer12"
	ti,timer-alwon;
	ti,timer-secure;
};
+18 −0
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@@ -2,9 +2,27 @@

properties:
- compatible : Should be "ti,omap-ocp2scp"
- reg : Address and length of the register set for the device
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ranges : the child address space are mapped 1:1 onto the parent address space
- ti,hwmods : must be "ocp2scp_usb_phy"

Sub-nodes:
All the devices connected to ocp2scp are described using sub-node to ocp2scp

ocp2scp@4a0ad000 {
	compatible = "ti,omap-ocp2scp";
	reg = <0x4a0ad000 0x1f>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,hwmods = "ocp2scp_usb_phy";

	subnode1 {
	...
	};

	subnode2 {
	...
	};
};
+2 −0
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@@ -55,5 +55,7 @@ st-micro,24c256 i2c serial eeprom (24cxx)
stm,m41t00		Serial Access TIMEKEEPER
stm,m41t62		Serial real-time clock (RTC) with alarm
stm,m41t80		M41T80 - SERIAL ACCESS RTC WITH ALARMS
taos,tsl2550		Ambient Light Sensor with SMBUS/Two Wire Serial Interface
ti,tsc2003		I2C Touch-Screen Controller
ti,tmp102		Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
ti,tmp275		Digital Temperature Sensor
+21 −0
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AM33XX MUSB GLUE
 - compatible : Should be "ti,musb-am33xx"
 - reg : offset and length of register sets, first usbss, then for musb instances
 - interrupts : usbss, musb instance interrupts in order
 - ti,hwmods : must be "usb_otg_hs"
 - multipoint : Should be "1" indicating the musb controller supports
   multipoint. This is a MUSB configuration-specific setting.
@@ -12,3 +14,22 @@ AM33XX MUSB GLUE
   represents PERIPHERAL.
 - power : Should be "250". This signifies the controller can supply upto
   500mA when operating in host mode.

Example:

usb@47400000  {
	compatible = "ti,musb-am33xx";
	reg = <0x47400000 0x1000	/* usbss */
	       0x47401000 0x800		/* musb instance 0 */
	       0x47401800 0x800>;	/* musb instance 1 */
	interrupts = <17		/* usbss */
		      18		/* musb instance 0 */
		      19>;		/* musb instance 1 */
	multipoint = <1>;
	num-eps = <16>;
	ram-bits = <12>;
	port0-mode = <3>;
	port1-mode = <3>;
	power = <250>;
	ti,hwmods = "usb_otg_hs";
};
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