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Commit c87cdfd2 authored by Nick Kossifidis's avatar Nick Kossifidis Committed by John W. Linville
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ath5k: Make some changes to follow register dumps. 



Make some changes which mimic what we see in register dumps.
This patch does not add a helper to ath5k_hw_reset(). It
does seem clear we need a re-shuffle around ath5k_hw_reset()
though as code in there is lengthy and already hitting 80-char
limit. This can be dealt with later though.

Changes-licensed-under: ISC
Signed-off-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarLuis R. Rodriguez <mcgrof@winlab.rutgers.edu>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 56c9054f

drivers/net/wireless/ath5k/hw.c

+31 −6
Original line number Original line Diff line number Diff line
@@ -724,15 +724,26 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, 
		/*

		/*

		 * Write some more initial register settings

		 * Write some more initial register settings

		 */

		 */

		if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */

		if (ah->ah_version == AR5K_AR5212) {

			ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));

			ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));





			if (channel->hw_value == CHANNEL_G)

			if (channel->hw_value == CHANNEL_G)

				ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */

				if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)

					ath5k_hw_reg_write(ah, 0x00f80d80,

						AR5K_PHY(83));

				else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)

					ath5k_hw_reg_write(ah, 0x00380140,

						AR5K_PHY(83));

				else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)

					ath5k_hw_reg_write(ah, 0x00fc0ec0,

						AR5K_PHY(83));

				else /* 2425 */

					ath5k_hw_reg_write(ah, 0x00fc0fc0,

						AR5K_PHY(83));

			else

			else

				ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));

				ath5k_hw_reg_write(ah, 0x00000000,

					AR5K_PHY(83));





			ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */

			ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);

			ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);

			ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);

			ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);

			ath5k_hw_reg_write(ah, 0x00000000, 0xa254);

			ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
@@ -1015,6 +1026,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, 




	/*

	/*

	 * Set the 32MHz reference clock on 5212 phy clock sleep register

	 * Set the 32MHz reference clock on 5212 phy clock sleep register

	 *

	 * TODO: Find out how to switch to external 32Khz clock to save power

	 */

	 */

	if (ah->ah_version == AR5K_AR5212) {

	if (ah->ah_version == AR5K_AR5212) {

		ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);

		ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
@@ -1025,6 +1038,14 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, 
		ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);

		ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);

	}

	}





	if (ah->ah_version == AR5K_AR5212) {

		ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);

		ath5k_hw_reg_write(ah, 0x00003210, 0x811c);

		ath5k_hw_reg_write(ah, 0x00000052, 0x8108);

		if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)

			ath5k_hw_reg_write(ah, 0x00000004, 0x8120);

	}



	/*

	/*

	 * Disable beacons and reset the register

	 * Disable beacons and reset the register

	 */

	 */
@@ -2269,8 +2290,8 @@ void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) 
	 * Set simple BSSID mask on 5212

	 * Set simple BSSID mask on 5212

	 */

	 */

	if (ah->ah_version == AR5K_AR5212) {

	if (ah->ah_version == AR5K_AR5212) {

		ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0);

		ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);

		ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1);

		ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);

	}

	}





	/*

	/*
@@ -2415,6 +2436,8 @@ void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 
{

{

	ATH5K_TRACE(ah->ah_sc);

	ATH5K_TRACE(ah->ah_sc);

	AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);

	AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);



	/* TODO: ANI Support */

}

}





/*

/*
@@ -2424,6 +2447,8 @@ void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah) 
{

{

	ATH5K_TRACE(ah->ah_sc);

	ATH5K_TRACE(ah->ah_sc);

	AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);

	AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);



	/* TODO: ANI Support */

}

}





/*

/*