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Commit c821c686 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Do a bit of cleanup in adreno-iommu 



Do some cleanup in the Adreno specific IOMMU code. Identify the
the functions that are a3xx specific and remove unused code paths.
This lets us get rid of one usage of cp_protected_mode and a now
unused adreno register.

Change-Id: Ic0dedbad9fcfd8be9c9eb20705fd7c19c0f94f6e
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent cfc1c286

drivers/gpu/msm/adreno.h

+0 −1
Original line number Diff line number Diff line
@@ -603,7 +603,6 @@ enum adreno_regs { 
	ADRENO_REG_CP_ME_RAM_DATA,

	ADRENO_REG_CP_PFP_UCODE_DATA,

	ADRENO_REG_CP_PFP_UCODE_ADDR,

	ADRENO_REG_CP_WFI_PEND_CTR,

	ADRENO_REG_CP_RB_BASE,

	ADRENO_REG_CP_RB_BASE_HI,

	ADRENO_REG_CP_RB_RPTR_ADDR_LO,

drivers/gpu/msm/adreno_a3xx.c

+0 −1
Original line number Diff line number Diff line
@@ -1232,7 +1232,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_DATA, A3XX_CP_ME_RAM_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_DATA, A3XX_CP_PFP_UCODE_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_ADDR, A3XX_CP_PFP_UCODE_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_WFI_PEND_CTR, A3XX_CP_WFI_PEND_CTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A3XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, ADRENO_REG_SKIP),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A3XX_CP_RB_RPTR),

drivers/gpu/msm/adreno_a5xx.c

+0 −1
Original line number Diff line number Diff line
@@ -2498,7 +2498,6 @@ static unsigned int a5xx_int_bits[ADRENO_INT_BITS_MAX] = { 


/* Register offset defines for A5XX, in order of enum adreno_regs */

static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_REG_CP_WFI_PEND_CTR, A5XX_CP_WFI_PEND_CTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A5XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, A5XX_CP_RB_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR_ADDR_LO,

drivers/gpu/msm/adreno_iommu.c

+22 −34
Original line number Diff line number Diff line
@@ -11,42 +11,30 @@ 
#include "adreno_pm4types.h"



/*

 * _wait_reg() - make CP poll on a register

 * a3xx_wait_reg() - make CP poll on a register

 * @cmds:	Pointer to memory where commands are to be added

 * @addr:	Register address to poll for

 * @val:	Value to poll for

 * @mask:	The value against which register value is masked

 * @interval:	wait interval

 */

static unsigned int _wait_reg(struct adreno_device *adreno_dev,

static unsigned int a3xx_wait_reg(struct adreno_device *adreno_dev,

			unsigned int *cmds, unsigned int addr,

			unsigned int val, unsigned int mask,

			unsigned int interval)

{

	unsigned int *start = cmds;



	if (adreno_is_a3xx(adreno_dev)) {

	*cmds++ = cp_packet(adreno_dev, CP_WAIT_REG_EQ, 4);

	*cmds++ = addr;

	*cmds++ = val;

	*cmds++ = mask;

	*cmds++ = interval;

	} else {

		*cmds++ = cp_mem_packet(adreno_dev, CP_WAIT_REG_MEM, 5, 1);

		*cmds++ = 0x3; /* Mem Space = Register,  Function = Equals */

		cmds += cp_gpuaddr(adreno_dev, cmds, addr); /* Poll address */

		*cmds++ = val; /* ref val */

		*cmds++ = mask;

		*cmds++ = interval;



		/* WAIT_REG_MEM turns back on protected mode - push it off */

		cmds += cp_protected_mode(adreno_dev, cmds, 0);

	}



	return cmds - start;

}



static unsigned int _vbif_lock(struct adreno_device *adreno_dev,

static unsigned int a3xx_vbif_lock(struct adreno_device *adreno_dev,

			unsigned int *cmds)

{

	unsigned int *start = cmds;
@@ -54,8 +42,7 @@ static unsigned int _vbif_lock(struct adreno_device *adreno_dev, 
	 * glue commands together until next

	 * WAIT_FOR_ME

	 */

	cmds += _wait_reg(adreno_dev, cmds,

			adreno_getreg(adreno_dev, ADRENO_REG_CP_WFI_PEND_CTR),

	cmds += a3xx_wait_reg(adreno_dev, cmds, A3XX_CP_WFI_PEND_CTR,

			1, 0xFFFFFFFF, 0xF);



	/* MMU-500 VBIF stall */
@@ -67,14 +54,14 @@ static unsigned int _vbif_lock(struct adreno_device *adreno_dev, 
	*cmds++ = 0x1;



	/* Wait for acknowledgment */

	cmds += _wait_reg(adreno_dev, cmds,

	cmds += a3xx_wait_reg(adreno_dev, cmds,

			A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1,

			1, 0xFFFFFFFF, 0xF);



	return cmds - start;

}



static unsigned int _vbif_unlock(struct adreno_device *adreno_dev,

static unsigned int a3xx_vbif_unlock(struct adreno_device *adreno_dev,

				unsigned int *cmds)

{

	unsigned int *start = cmds;
@@ -95,7 +82,7 @@ static unsigned int _vbif_unlock(struct adreno_device *adreno_dev, 
#define A3XX_GPU_OFFSET 0xa000



/* This function is only needed for A3xx targets */

static unsigned int _cp_smmu_reg(struct adreno_device *adreno_dev,

static unsigned int a3xx_cp_smmu_reg(struct adreno_device *adreno_dev,

				unsigned int *cmds,

				enum kgsl_iommu_reg_map reg,

				unsigned int num)
@@ -110,20 +97,20 @@ static unsigned int _cp_smmu_reg(struct adreno_device *adreno_dev, 
}



/* This function is only needed for A3xx targets */

static unsigned int _tlbiall(struct adreno_device *adreno_dev,

static unsigned int a3xx_tlbiall(struct adreno_device *adreno_dev,

				unsigned int *cmds)

{

	unsigned int *start = cmds;

	unsigned int tlbstatus = (A3XX_GPU_OFFSET +

		kgsl_iommu_reg_list[KGSL_IOMMU_CTX_TLBSTATUS]) >> 2;



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TLBIALL, 1);

	cmds += a3xx_cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TLBIALL, 1);

	*cmds++ = 1;



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TLBSYNC, 1);

	cmds += a3xx_cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TLBSYNC, 1);

	*cmds++ = 0;



	cmds += _wait_reg(adreno_dev, cmds, tlbstatus, 0,

	cmds += a3xx_wait_reg(adreno_dev, cmds, tlbstatus, 0,

			KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE, 0xF);



	return cmds - start;
@@ -205,17 +192,18 @@ static unsigned int _adreno_iommu_set_pt_v2_a3xx(struct kgsl_device *device, 


	cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);



	cmds += _vbif_lock(adreno_dev, cmds);

	cmds += a3xx_vbif_lock(adreno_dev, cmds);



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	cmds += a3xx_cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_CONTEXTIDR, 1);

	cmds += a3xx_cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_CONTEXTIDR,

		1);

	*cmds++ = contextidr;



	cmds += _vbif_unlock(adreno_dev, cmds);

	cmds += a3xx_vbif_unlock(adreno_dev, cmds);



	cmds += _tlbiall(adreno_dev, cmds);

	cmds += a3xx_tlbiall(adreno_dev, cmds);



	/* wait for me to finish the TLBI */

	cmds += cp_wait_for_me(adreno_dev, cmds);