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Commit c7ae7e9a authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnl: Configure EU slice power gating. 



Cannonlake also supports slice power gating on devices with more
than one slice as SKL. Let's assume that this is the same for SKL+
and exclude BXT only.

v2: Also remove KBL.

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-7-git-send-email-rodrigo.vivi@intel.com
parent 8366be98

drivers/gpu/drm/i915/intel_device_info.c

+3 −4
Original line number Diff line number Diff line
@@ -184,16 +184,15 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 
				DIV_ROUND_UP(sseu->eu_total,

					     sseu_subslice_total(sseu)) : 0;

	/*

	 * SKL supports slice power gating on devices with more than

	 * SKL+ supports slice power gating on devices with more than

	 * one slice, and supports EU power gating on devices with

	 * more than one EU pair per subslice. BXT supports subslice

	 * more than one EU pair per subslice. BXT+ supports subslice

	 * power gating on devices with more than one subslice, and

	 * supports EU power gating on devices with more than one EU

	 * pair per subslice.

	*/

	sseu->has_slice_pg =

		(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

		hweight8(sseu->slice_mask) > 1;

		!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;

	sseu->has_subslice_pg =

		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;

	sseu->has_eu_pg = sseu->eu_per_subslice > 2;