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Commit c791bbbf authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
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ARM: imx: add L2 page power control for GPC 



Some platforms like i.MX6UL/i.MX6SLL have L2
page power control in GPC, it needs to be
disabled if ARM is power gated and L2 is NOT
flushed, add GPC interface to control it.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 22021948

arch/arm/mach-imx/common.h

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ struct device *imx_soc_device_init(void); 
void imx6_enable_rbc(bool enable);

void imx_gpc_check_dt(void);

void imx_gpc_set_arm_power_in_lpm(bool power_off);

void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);

void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);

void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);

void imx25_pm_init(void);

arch/arm/mach-imx/gpc.c

+14 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include "common.h"

#include "hardware.h"



#define GPC_CNTR		0x0

#define GPC_IMR1		0x008

#define GPC_PGC_CPU_PDN		0x2a0

#define GPC_PGC_CPU_PUPSCR	0x2a4
@@ -27,6 +28,8 @@ 
#define GPC_PGC_SW2ISO_SHIFT	0x8

#define GPC_PGC_SW_SHIFT	0x0



#define GPC_CNTR_L2_PGE_SHIFT	22



#define IMR_NUM			4

#define GPC_MAX_IRQS		(IMR_NUM * 32)
@@ -51,6 +54,17 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off) 
	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);

}



void imx_gpc_set_l2_mem_power_in_lpm(bool power_off)

{

	u32 val;



	val = readl_relaxed(gpc_base + GPC_CNTR);

	val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT);

	if (power_off)

		val |= 1 << GPC_CNTR_L2_PGE_SHIFT;

	writel_relaxed(val, gpc_base + GPC_CNTR);

}



void imx_gpc_pre_suspend(bool arm_power_off)

{

	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;