net: ethernet: stmmac: Clean up dead code

#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x)	1

#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x)	((x >= 2) ? 1 : 0)

#define NSS_COMMON_MACSEC_CTL			0x28

#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x)	(1 << x)

#define NSS_COMMON_GMAC_CTL(x)			(0x30 + (x * 4))

#define NSS_COMMON_GMAC_CTL_CSYS_REQ		BIT(19)

#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL	BIT(16)

#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET	8

#define NSS_COMMON_GMAC_CTL_IFG_OFFSET		0

#define NSS_COMMON_GMAC_CTL_IFG_MASK		0x3f

#define NSS_COMMON_CLK_DIV_RGMII_1000		1

#define NSS_COMMON_CLK_DIV_RGMII_100		9

#define NSS_COMMON_CLK_DIV_SGMII_100		4

#define NSS_COMMON_CLK_DIV_SGMII_10		49

#define QSGMII_PCS_MODE_CTL			0x68

#define QSGMII_PCS_MODE_CTL_AUTONEG_EN(x)	BIT((x * 8) + 7)

#define QSGMII_PCS_CAL_LCKDT_CTL		0x120

#define QSGMII_PCS_CAL_LCKDT_CTL_RST		BIT(19)

#define QSGMII_PHY_TX_DRIVER_EN			BIT(3)

#define QSGMII_PHY_QSGMII_EN			BIT(7)

#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET	12

#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK		0x7

#define QSGMII_PHY_RX_DC_BIAS_OFFSET		18

#define QSGMII_PHY_RX_DC_BIAS_MASK		0x3

#define QSGMII_PHY_RX_INPUT_EQU_OFFSET		20

#define QSGMII_PHY_RX_INPUT_EQU_MASK		0x3

#define QSGMII_PHY_CDR_PI_SLEW_OFFSET		22

#define QSGMII_PHY_CDR_PI_SLEW_MASK		0x3

#define QSGMII_PHY_TX_DRV_AMP_OFFSET		28

#define QSGMII_PHY_TX_DRV_AMP_MASK		0xf

struct ipq806x_gmac {

	struct platform_device *pdev;

	 * code and keep it consistent with the Linux convention, we'll number

	 * them from 0 to 3 here.

	 */

	if (gmac->id < 0 || gmac->id > 3) {

	if (gmac->id > 3) {

		dev_err(dev, "invalid gmac id\n");

		return -EINVAL;

	}