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Commit c747f97c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm amd fixes from Dave Airlie:
 "Been pretty quiet.

  This is an amdgpu fixes pull from AMD, a bunch of powerplay stability
  fixes, race fix, hibernate fix, and a possible circular locking fix"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (21 commits)
  drm/amdgpu: fix issue with overlapping userptrs
  drm/radeon: hold reference to fences in radeon_sa_bo_new
  drm/amdgpu: remove unnecessary forward declaration
  drm/amdgpu: hold reference to fences in amdgpu_sa_bo_new (v2)
  drm/amdgpu: fix s4 resume
  drm/amdgpu/cz: plumb pg flags through to powerplay
  drm/amdgpu/tonga: plumb pg flags through to powerplay
  drma/dmgpu: move cg and pg flags into shared headers
  drm/amdgpu: remove unused cg defines
  drm/amdgpu: add a cgs interface to fetch cg and pg flags
  drm/amd/powerplay/tonga: disable vce pg
  drm/amd/powerplay/tonga: disable uvd pg
  drm/amd/powerplay/cz: disable vce pg
  drm/amd/powerplay/cz: disable uvd pg
  drm/amdgpu: be consistent with uvd cg flags
  drm/amdgpu: clean up vce pg flags for cz/st
  drm/amdgpu: handle vce pg flags properly
  drm/amdgpu: handle uvd pg flags properly
  drm/amdgpu/dpm/ci: switch over to the common pcie caps interface
  drm/amdgpu/cik: don't mess with aspm if gpu is root bus
  ...
parents df8c2723 c92a428f

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −43
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs; 
extern int amdgpu_sched_hw_submission;

extern int amdgpu_enable_semaphores;

extern int amdgpu_powerplay;

extern unsigned amdgpu_pcie_gen_cap;

extern unsigned amdgpu_pcie_lane_cap;



#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
@@ -132,47 +134,6 @@ extern int amdgpu_powerplay; 
#define AMDGPU_RESET_VCE			(1 << 13)

#define AMDGPU_RESET_VCE1			(1 << 14)



/* CG block flags */

#define AMDGPU_CG_BLOCK_GFX			(1 << 0)

#define AMDGPU_CG_BLOCK_MC			(1 << 1)

#define AMDGPU_CG_BLOCK_SDMA			(1 << 2)

#define AMDGPU_CG_BLOCK_UVD			(1 << 3)

#define AMDGPU_CG_BLOCK_VCE			(1 << 4)

#define AMDGPU_CG_BLOCK_HDP			(1 << 5)

#define AMDGPU_CG_BLOCK_BIF			(1 << 6)



/* CG flags */

#define AMDGPU_CG_SUPPORT_GFX_MGCG		(1 << 0)

#define AMDGPU_CG_SUPPORT_GFX_MGLS		(1 << 1)

#define AMDGPU_CG_SUPPORT_GFX_CGCG		(1 << 2)

#define AMDGPU_CG_SUPPORT_GFX_CGLS		(1 << 3)

#define AMDGPU_CG_SUPPORT_GFX_CGTS		(1 << 4)

#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)

#define AMDGPU_CG_SUPPORT_GFX_CP_LS		(1 << 6)

#define AMDGPU_CG_SUPPORT_GFX_RLC_LS		(1 << 7)

#define AMDGPU_CG_SUPPORT_MC_LS			(1 << 8)

#define AMDGPU_CG_SUPPORT_MC_MGCG		(1 << 9)

#define AMDGPU_CG_SUPPORT_SDMA_LS		(1 << 10)

#define AMDGPU_CG_SUPPORT_SDMA_MGCG		(1 << 11)

#define AMDGPU_CG_SUPPORT_BIF_LS		(1 << 12)

#define AMDGPU_CG_SUPPORT_UVD_MGCG		(1 << 13)

#define AMDGPU_CG_SUPPORT_VCE_MGCG		(1 << 14)

#define AMDGPU_CG_SUPPORT_HDP_LS		(1 << 15)

#define AMDGPU_CG_SUPPORT_HDP_MGCG		(1 << 16)



/* PG flags */

#define AMDGPU_PG_SUPPORT_GFX_PG		(1 << 0)

#define AMDGPU_PG_SUPPORT_GFX_SMG		(1 << 1)

#define AMDGPU_PG_SUPPORT_GFX_DMG		(1 << 2)

#define AMDGPU_PG_SUPPORT_UVD			(1 << 3)

#define AMDGPU_PG_SUPPORT_VCE			(1 << 4)

#define AMDGPU_PG_SUPPORT_CP			(1 << 5)

#define AMDGPU_PG_SUPPORT_GDS			(1 << 6)

#define AMDGPU_PG_SUPPORT_RLC_SMU_HS		(1 << 7)

#define AMDGPU_PG_SUPPORT_SDMA			(1 << 8)

#define AMDGPU_PG_SUPPORT_ACP			(1 << 9)

#define AMDGPU_PG_SUPPORT_SAMU			(1 << 10)



/* GFX current status */

#define AMDGPU_GFX_NORMAL_MODE			0x00000000L

#define AMDGPU_GFX_SAFE_MODE			0x00000001L
@@ -606,8 +567,6 @@ struct amdgpu_sa_manager { 
	uint32_t		align;

};



struct amdgpu_sa_bo;



/* sub-allocation buffer */

struct amdgpu_sa_bo {

	struct list_head		olist;
@@ -2360,6 +2319,8 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,

				     uint32_t flags);

bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);

bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,

				  unsigned long end);

bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);

uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,

				 struct ttm_mem_reg *mem);

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+6 −0
Original line number Diff line number Diff line
@@ -795,6 +795,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device, 
	case CGS_SYSTEM_INFO_PCIE_MLW:

		sys_info->value = adev->pm.pcie_mlw_mask;

		break;

	case CGS_SYSTEM_INFO_CG_FLAGS:

		sys_info->value = adev->cg_flags;

		break;

	case CGS_SYSTEM_INFO_PG_FLAGS:

		sys_info->value = adev->pg_flags;

		break;

	default:

		return -ENODEV;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+91 −69
Original line number Diff line number Diff line
@@ -1795,15 +1795,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 
	}



	/* post card */

	if (!amdgpu_card_posted(adev))

		amdgpu_atom_asic_init(adev->mode_info.atom_context);



	r = amdgpu_resume(adev);

	if (r)

		DRM_ERROR("amdgpu_resume failed (%d).\n", r);



	amdgpu_fence_driver_resume(adev);



	if (resume) {

		r = amdgpu_ib_ring_tests(adev);

		if (r)

			DRM_ERROR("ib ring test failed (%d).\n", r);

	}



	r = amdgpu_late_init(adev);

	if (r)
@@ -1933,20 +1938,30 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) 
	return r;

}



#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */

#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */



void amdgpu_get_pcie_info(struct amdgpu_device *adev)

{

	u32 mask;

	int ret;



	if (pci_is_root_bus(adev->pdev->bus))

		return;

	if (amdgpu_pcie_gen_cap)

		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;



	if (amdgpu_pcie_gen2 == 0)

		return;

	if (amdgpu_pcie_lane_cap)

		adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;



	if (adev->flags & AMD_IS_APU)

	/* covers APUs as well */

	if (pci_is_root_bus(adev->pdev->bus)) {

		if (adev->pm.pcie_gen_mask == 0)

			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;

		if (adev->pm.pcie_mlw_mask == 0)

			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;

		return;

	}



	if (adev->pm.pcie_gen_mask == 0) {

		ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);

		if (!ret) {

			adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
@@ -1959,7 +1974,11 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev) 
				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;

			if (mask & DRM_PCIE_SPEED_80)

				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;

		} else {

			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;

		}

	}

	if (adev->pm.pcie_mlw_mask == 0) {

		ret = drm_pcie_get_max_link_width(adev->ddev, &mask);

		if (!ret) {

			switch (mask) {
@@ -2008,6 +2027,9 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev) 
			default:

				break;

			}

		} else {

			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;

		}

	}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+8 −0
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32; 
int amdgpu_sched_hw_submission = 2;

int amdgpu_enable_semaphores = 0;

int amdgpu_powerplay = -1;

unsigned amdgpu_pcie_gen_cap = 0;

unsigned amdgpu_pcie_lane_cap = 0;



MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");

module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = 
module_param_named(powerplay, amdgpu_powerplay, int, 0444);

#endif



MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");

module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);



MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");

module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);



static struct pci_device_id pciidlist[] = {

#ifdef CONFIG_DRM_AMDGPU_CIK

	/* Kaveri */

drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c

+2 −1
Original line number Diff line number Diff line
@@ -142,7 +142,8 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, 


		list_for_each_entry(bo, &node->bos, mn_list) {



			if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)

			if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start,

							  end))

				continue;



			r = amdgpu_bo_reserve(bo, true);