Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c73dbd71 authored by Sascha Hauer's avatar Sascha Hauer Committed by Shawn Guo
Browse files

ARM: dts: i.MX51 babbage: Fix FEC pad ctrl settings 



The dts relied on the FEC pad ctrl settings from the bootloader by
using the NO_PAD_CTRL option. This breaks once the bootloader starts
initializing the pad ctrl settings from the same dts file. Change
to real pad ctrl settings taken from the platform based babbage
support.

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent e02ab39a

arch/arm/boot/dts/imx51-babbage.dts

+19 −18
Original line number Diff line number Diff line
@@ -488,24 +488,25 @@ 


		pinctrl_fec: fecgrp {

			fsl,pins = <

				MX51_PAD_EIM_EB2__FEC_MDIO		0x80000000

				MX51_PAD_EIM_EB3__FEC_RDATA1		0x80000000

				MX51_PAD_EIM_CS2__FEC_RDATA2		0x80000000

				MX51_PAD_EIM_CS3__FEC_RDATA3		0x80000000

				MX51_PAD_EIM_CS4__FEC_RX_ER		0x80000000

				MX51_PAD_EIM_CS5__FEC_CRS		0x80000000

				MX51_PAD_NANDF_RB2__FEC_COL		0x80000000

				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x80000000

				MX51_PAD_NANDF_D9__FEC_RDATA0		0x80000000

				MX51_PAD_NANDF_D8__FEC_TDATA0		0x80000000

				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x80000000

				MX51_PAD_NANDF_CS3__FEC_MDC		0x80000000

				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x80000000

				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x80000000

				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x80000000

				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x80000000

				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x80000000

				MX51_PAD_EIM_A20__GPIO2_14		0x85 /* Reset */

				MX51_PAD_EIM_EB2__FEC_MDIO		0x000001f5

				MX51_PAD_EIM_EB3__FEC_RDATA1		0x00000085

				MX51_PAD_EIM_CS2__FEC_RDATA2		0x00000085

				MX51_PAD_EIM_CS3__FEC_RDATA3		0x00000085

				MX51_PAD_EIM_CS4__FEC_RX_ER		0x00000180

				MX51_PAD_EIM_CS5__FEC_CRS		0x00000180

				MX51_PAD_NANDF_RB2__FEC_COL		0x00000180

				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x00000180

				MX51_PAD_NANDF_D9__FEC_RDATA0		0x00002180

				MX51_PAD_NANDF_D8__FEC_TDATA0		0x00002004

				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x00002004

				MX51_PAD_NANDF_CS3__FEC_MDC		0x00002004

				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x00002004

				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x00002004

				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x00002004

				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x00002004

				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x00002180

				MX51_PAD_NANDF_D11__FEC_RX_DV		0x000020a4

				MX51_PAD_EIM_A20__GPIO2_14		0x00000085 /* Phy Reset */

			>;

		};