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Commit c7149867 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add default pinctrl state for LAGOON HSUART"

parents 0b01d1e2 5060afad

qcom/lagoon-pinctrl.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -197,6 +197,32 @@ 
		};



		qupv3_se1_4uart_pins: qupv3_se1_4uart_pins {

			qupv3_se1_default_ctsrtsrx: qupv3_se1_default_ctsrtsrx {

				mux {

					pins = "gpio61", "gpio62", "gpio64";

					function = "gpio";

				};



				config {

					pins = "gpio61", "gpio62", "gpio64";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se1_default_tx: qupv3_se1_default_tx {

				mux {

					pins = "gpio63";

					function = "gpio";

				};



				config {

					pins = "gpio63";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se1_ctsrx: qupv3_se1_ctsrx {

				mux {

					pins = "gpio61", "gpio64";

qcom/lagoon-qupv3.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -99,11 +99,13 @@ 
		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,

						<&qupv3_se1_tx>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se1_default_ctsrtsrx>,

				<&qupv3_se1_default_tx>;

		pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,

						<&qupv3_se1_tx>;

		pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,

						<&qupv3_se1_tx>;

		interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,

				<&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;