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Commit c6ed444f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v4.19:

  Core changes:

   - Augment pinctrl_generic_add_group() and pinmux_generic_add_function()
     to return the selector for the added group/function to the caller
     and augment (hopefully) all drivers to handle this

  New subdrivers:

   - Qualcomm PM8998 and PM8005 are supported in the SPMI pin control
     and GPIO driver

   - Intel Ice Lake PCH (platform controller hub) support

   - NXP (ex Freescale) i.MX8MQ support

   - Berlin AS370 support

  Improvements to drivers:

   - Support interrupts on the Ocelot pin controller

   - Add SPI pins to the Uniphier driver

   - Define a GPIO compatible per SoC in the Tegra driver

   - Push Tegra initialization down in the initlevels

   - Support external wakeup interrupts on the Exynos

   - Add generic clocks pins to the meson driver

   - Add USB and HSCIF pins for some Renesas PFC chips

   - Suspend/resume support in the armada-37xx

   - Interrupt support for the Actions Semiconductor S900 also known as
     "owl"

   - Correct the pin ordering in Cedarfork

   - Debugfs output for INTF in the mcp23s08 driver

   - Avoid divisions in context save/restore in pinctrl-single

  The rest is minor bug fixes or cleanups"

* tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (69 commits)
  pinctrl: nomadik: silence uninitialized variable warning
  pinctrl: axp209: Fix NULL pointer dereference after allocation
  pinctrl: samsung: Remove duplicated "wakeup" in printk
  pinctrl: ocelot: add support for interrupt controller
  pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq()
  pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state
  gpio: tegra: Move driver registration to subsys_init level
  pinctrl: tegra: Move drivers registration to arch_init level
  pinctrl: baytrail: actually print the apparently misconfigured pin
  MAINTAINERS: Replace Heikki as maintainer of Intel pinctrl
  pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show()
  pinctrl: uniphier: add spi pin-mux settings
  pinctrl: cannonlake: Fix community ordering for H variant
  pinctrl: tegra: define GPIO compatible node per SoC
  pinctrl: intel: Do pin translation when lock IRQ
  pinctrl: imx: off by one in imx_pinconf_group_dbg_show()
  pinctrl: mediatek: include chained_irq.h header
  pinctrl/amd: only handle irq if it is pending and unmasked
  pinctrl/amd: fix gpio irq level in debugfs
  pinctrl: stm32: add syscfg mask parameter
  ...
parents 3860cae6 c2944a9a

Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt

+10 −0
Original line number Diff line number Diff line
@@ -19,6 +19,10 @@ Required Properties: 
                    defines the interrupt number, the second encodes

                    the trigger flags described in

                    bindings/interrupt-controller/interrupts.txt

- interrupts: The interrupt outputs from the controller. There is one GPIO

              interrupt per GPIO bank. The number of interrupts listed depends

              on the number of GPIO banks on the SoC. The interrupts must be

              ordered by bank, starting with bank 0.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the
@@ -180,6 +184,12 @@ Example: 
                  #gpio-cells = <2>;

                  interrupt-controller;

                  #interrupt-cells = <2>;

                  interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

                               <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

                               <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

                               <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

                               <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;



                  uart2-default: uart2-default {

                          pinmux {

Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt

+3 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ Optional properties: 
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,

bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,

input-debounce, output-low, output-high.

- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for

high drive. The default value is low drive.



Example:
@@ -66,6 +68,7 @@ Example: 
			pinmux = <PIN_PB0>,

				 <PIN_PB5>;

			bias-pull-up;

			atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;

		};



		pinctrl_sdmmc1_default: sdmmc1_default {

Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt

+2 −1
Original line number Diff line number Diff line
@@ -23,7 +23,8 @@ Required properties: 
	"marvell,berlin2q-system-pinctrl",

	"marvell,berlin4ct-avio-pinctrl",

	"marvell,berlin4ct-soc-pinctrl",

	"marvell,berlin4ct-system-pinctrl"

	"marvell,berlin4ct-system-pinctrl",

	"syna,as370-soc-pinctrl"



Required subnode-properties:

- groups: a list of strings describing the group names.

Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
* Freescale IMX8MQ IOMUX Controller



Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

for common binding part and usage.



Required properties:

- compatible: "fsl,imx8mq-iomuxc"

- reg: should contain the base physical address and size of the iomuxc

  registers.



Required properties in sub-nodes:

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  imx8mq-pinfunc.h under device tree source folder.  The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Quad

  Reference Manual for detailed CONFIG settings.



Examples:



&uart1 {

       pinctrl-names = "default";

       pinctrl-0 = <&pinctrl_uart1>;

};



iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mq-iomuxc";

        reg = <0x0 0x30330000 0x0 0x10000>;



        pinctrl_uart1: uart1grp {

                fsl,pins = <

                        MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49

                        MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49

                >;

        };

};

Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt

+6 −0
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ Required properties: 
- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.

- gpio-ranges: see ../gpio/gpio.txt



Optional properties:



- gpio-reserved-ranges: see ../gpio/gpio.txt



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.
@@ -67,6 +72,7 @@ Example: 


		pinctrl-names = "default";

		pinctrl-0 = <&gsbi5_uart_default>;

		gpio-ranges = <&msmgpio 0 0 90>;



		gsbi5_uart_default: gsbi5_uart_default {

			mux {