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Commit c6c4696f authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers 



For internal APIs passing dev_priv is preferred to reduce indirections,
so convert over a few DDI PHY, CDCLK helpers.

No functional change.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Acked-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-10-git-send-email-imre.deak@intel.com
parent 443a93ac

drivers/gpu/drm/i915/i915_drv.c

+4 −8
Original line number Diff line number Diff line
@@ -1080,12 +1080,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv) 


static int bxt_suspend_complete(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;



	/* TODO: when DC5 support is added disable DC5 here. */



	broxton_ddi_phy_uninit(dev);

	broxton_uninit_cdclk(dev);

	broxton_ddi_phy_uninit(dev_priv);

	broxton_uninit_cdclk(dev_priv);

	bxt_enable_dc9(dev_priv);



	return 0;
@@ -1093,8 +1091,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv) 


static int bxt_resume_prepare(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;



	/* TODO: when CSR FW support is added make sure the FW is loaded */



	bxt_disable_dc9(dev_priv);
@@ -1103,8 +1099,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) 
	 * TODO: when DC5 support is added enable DC5 here if the CSR FW

	 * is available.

	 */

	broxton_init_cdclk(dev);

	broxton_ddi_phy_init(dev);

	broxton_init_cdclk(dev_priv);

	broxton_ddi_phy_init(dev_priv);



	return 0;

}

drivers/gpu/drm/i915/intel_ddi.c

+4 −6
Original line number Diff line number Diff line
@@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, 
	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);

}



void broxton_ddi_phy_init(struct drm_device *dev)

void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)

{

	/* Enable PHY1 first since it provides Rcomp for PHY0 */

	broxton_phy_init(dev->dev_private, DPIO_PHY1);

	broxton_phy_init(dev->dev_private, DPIO_PHY0);

	broxton_phy_init(dev_priv, DPIO_PHY1);

	broxton_phy_init(dev_priv, DPIO_PHY0);

}



static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
@@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 
	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);

}



void broxton_ddi_phy_uninit(struct drm_device *dev)

void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	broxton_phy_uninit(dev_priv, DPIO_PHY1);

	broxton_phy_uninit(dev_priv, DPIO_PHY0);

drivers/gpu/drm/i915/intel_display.c

+7 −11
Original line number Diff line number Diff line
@@ -5328,9 +5328,8 @@ static void intel_update_cdclk(struct drm_device *dev) 
		intel_update_max_cdclk(dev);

}



static void broxton_set_cdclk(struct drm_device *dev, int frequency)

static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t divider;

	uint32_t ratio;

	uint32_t current_freq;
@@ -5444,12 +5443,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency) 
		return;

	}



	intel_update_cdclk(dev);

	intel_update_cdclk(dev_priv->dev);

}



void broxton_init_cdclk(struct drm_device *dev)

void broxton_init_cdclk(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t val;



	/*
@@ -5478,7 +5476,7 @@ void broxton_init_cdclk(struct drm_device *dev) 
	 * - check if setting the max (or any) cdclk freq is really necessary

	 *   here, it belongs to modeset time

	 */

	broxton_set_cdclk(dev, 624000);

	broxton_set_cdclk(dev_priv, 624000);



	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);

	POSTING_READ(DBUF_CTL);
@@ -5489,10 +5487,8 @@ void broxton_init_cdclk(struct drm_device *dev) 
		DRM_ERROR("DBuf power enable timeout!\n");

}



void broxton_uninit_cdclk(struct drm_device *dev)

void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);

	POSTING_READ(DBUF_CTL);
@@ -5502,7 +5498,7 @@ void broxton_uninit_cdclk(struct drm_device *dev) 
		DRM_ERROR("DBuf power disable timeout!\n");



	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */

	broxton_set_cdclk(dev, 19200);

	broxton_set_cdclk(dev_priv, 19200);



	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);

}
@@ -9536,7 +9532,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) 
		to_intel_atomic_state(old_state);

	unsigned int req_cdclk = old_intel_state->dev_cdclk;



	broxton_set_cdclk(dev, req_cdclk);

	broxton_set_cdclk(to_i915(dev), req_cdclk);

}



/* compute the max rate for new configuration */

drivers/gpu/drm/i915/intel_dpll_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -1653,8 +1653,8 @@ static void intel_ddi_pll_init(struct drm_device *dev) 
		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))

			DRM_ERROR("LCPLL1 is disabled\n");

	} else if (IS_BROXTON(dev)) {

		broxton_init_cdclk(dev);

		broxton_ddi_phy_init(dev);

		broxton_init_cdclk(dev_priv);

		broxton_ddi_phy_init(dev_priv);

	} else {

		/*

		 * The LCPLL register should be turned on by the BIOS. For now

drivers/gpu/drm/i915/intel_drv.h

+4 −4
Original line number Diff line number Diff line
@@ -1224,10 +1224,10 @@ void intel_prepare_reset(struct drm_device *dev); 
void intel_finish_reset(struct drm_device *dev);

void hsw_enable_pc8(struct drm_i915_private *dev_priv);

void hsw_disable_pc8(struct drm_i915_private *dev_priv);

void broxton_init_cdclk(struct drm_device *dev);

void broxton_uninit_cdclk(struct drm_device *dev);

void broxton_ddi_phy_init(struct drm_device *dev);

void broxton_ddi_phy_uninit(struct drm_device *dev);

void broxton_init_cdclk(struct drm_i915_private *dev_priv);

void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);

void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);

void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);

void bxt_enable_dc9(struct drm_i915_private *dev_priv);

void bxt_disable_dc9(struct drm_i915_private *dev_priv);

void skl_init_cdclk(struct drm_i915_private *dev_priv);