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Commit c6b9f7b6 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: correct cached PCIe link BW max gen speed 



PCIe link BW (bandwidth) max GEN speed is incorrectly calculated.
Update bw_gen_max to have to the correct value.

Change-Id: I5a9c77e326966681bdc0efde84815dcea083d470
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 506b4826

drivers/pci/controller/pci-msm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -3740,7 +3740,7 @@ static int msm_pcie_get_bw_scale(struct msm_pcie_dev_t *pcie_dev) 
		of_property_read_u32_array(pdev->dev.of_node, "qcom,bw-scale",

		of_property_read_u32_array(pdev->dev.of_node, "qcom,bw-scale",

				(u32 *)pcie_dev->bw_scale, size / sizeof(u32));

				(u32 *)pcie_dev->bw_scale, size / sizeof(u32));





		pcie_dev->bw_gen_max = size / sizeof(u32);

		pcie_dev->bw_gen_max = size / sizeof(*pcie_dev->bw_scale);

	} else {

	} else {

		PCIE_DBG(pcie_dev, "RC%d: bandwidth scaling is not supported\n",

		PCIE_DBG(pcie_dev, "RC%d: bandwidth scaling is not supported\n",

			pcie_dev->rc_idx);

			pcie_dev->rc_idx);