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Commit c6945455 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix calibration for AR9462 



TX IQ calibration is disabled by default for AR9462, this
is done using the initvals (reg 0xa644).

But, to compensate for this, the AR_PHY_RX_DELAY register
should be set to the max allowed value when performing
calibration.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 8aee318f

drivers/net/wireless/ath/ath9k/ar9003_calib.c

+15 −0
Original line number Diff line number Diff line
@@ -1019,6 +1019,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, 
	bool is_reusable = true, status = true;

	bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;

	bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);

	u32 rx_delay = 0;

	u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |

					  AR_PHY_AGC_CONTROL_FLTR_CAL   |

					  AR_PHY_AGC_CONTROL_PKDET_CAL;
@@ -1099,6 +1100,15 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, 
		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

	}



	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

		rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);

		/* Disable BB_active */

		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);

		udelay(5);

		REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);

		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

	}



	if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {

		/* Calibrate the AGC */

		REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -1113,6 +1123,11 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, 
		ar9003_hw_do_manual_peak_cal(ah, chan);

	}



	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

		REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);

		udelay(5);

	}



	if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)

		ar9003_mci_init_cal_done(ah);