Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c5dcfe65 authored by Kieran Bingham's avatar Kieran Bingham Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a7795: Fix register mappings on VSPs 



The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent d9366032

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -2208,7 +2208,7 @@ 


		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x4000>;

			reg = <0 0xfea20000 0 0x8000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2228,7 +2228,7 @@ 


		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x4000>;

			reg = <0 0xfea28000 0 0x8000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2248,7 +2248,7 @@ 


		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x4000>;

			reg = <0 0xfea30000 0 0x8000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;