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Commit c5a790aa authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Fixes warnings in kona device tree"

parents ee19f9ba 5a1428b7

arch/arm64/boot/dts/qcom/kona-ion.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -9,13 +9,13 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		system_heap: qcom,ion-heap@25 {

			reg = <25>;

		system_heap: qcom,ion-heap@19 {

			reg = <0x19>;

			qcom,ion-heap-type = "SYSTEM";

		};



		system_secure_heap: qcom,ion-heap@9 {

			reg = <9>;

			reg = <0x9>;

			qcom,ion-heap-type = "SYSTEM_SECURE";

		};

	};

arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 */



&soc {

	tlmm: pinctrl@0F000000 {

	tlmm: pinctrl@f000000 {

		compatible = "qcom,kona-pinctrl";

		reg = <0x0F000000 0x1000000>;

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -76,6 +76,7 @@ 
					bias-disable;

				};

			};



			ap2mdm_sleep: ap2mdm_sleep {

				mux {

					/* ap2mdm-status
@@ -112,6 +113,7 @@ 
					bias-disable;

				};

			};



			mdm2ap_sleep: mdm2ap_sleep {

				mux {

					/* mdm2ap-status

arch/arm64/boot/dts/qcom/kona-rumi.dtsi

+6 −8
Original line number Diff line number Diff line
@@ -3,15 +3,13 @@ 
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



&soc {

	timer {

&arch_timer {

	clock-frequency = <1000000>;

};



	timer@0x17c00000 {

&memtimer {

	clock-frequency = <1000000>;

};

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qrbtc-sdm845";

arch/arm64/boot/dts/qcom/kona.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -364,7 +364,7 @@ 
		reg-names = "llcc_base", "llcc_broadcast_base";

	};



	timer {

	arch_timer: timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -373,7 +373,7 @@ 
		clock-frequency = <19200000>;

	};



	timer@0x17c20000{

	memtimer: timer@17c20000 {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -381,7 +381,7 @@ 
		reg = <0x17c20000 0x1000>;

		clock-frequency = <19200000>;



		frame@0x17c21000 {

		frame@17c21000 {

			frame-number = <0>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -417,7 +417,7 @@ 
			status = "disabled";

		};



		frame@17c2b0000 {

		frame@17c2b000 {

			frame-number = <5>;

			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x17c2b000 0x1000>;
@@ -441,7 +441,7 @@ qcom,msm-imem@146bf000 { 


		restart_reason@65c {

			compatible = "qcom,msm-imem-restart_reason";

			reg = <0x65c 4>;

			reg = <0x65c 0x4>;

		};



		dload_type@1c {
@@ -451,17 +451,17 @@ qcom,msm-imem@146bf000 { 


		boot_stats@6b0 {

			compatible = "qcom,msm-imem-boot_stats";

			reg = <0x6b0 32>;

			reg = <0x6b0 0x20>;

		};



		kaslr_offset@6d0 {

			compatible = "qcom,msm-imem-kaslr_offset";

			reg = <0x6d0 12>;

			reg = <0x6d0 0xc>;

		};



		pil@94c {

			compatible = "qcom,msm-imem-pil";

			reg = <0x94c 200>;

			reg = <0x94c 0xc8>;

		};

	};
@@ -719,7 +719,7 @@ qcom,msm-imem@146bf000 { 
		mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;

	};



	apps_rsc: rsc@0x18200000 {

	apps_rsc: rsc@18200000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";

		reg = <0x18200000 0x10000>,

arch/arm64/boot/dts/qcom/msm-arm-smmu-kona.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>



&soc {

	kgsl_smmu: kgsl-smmu@0x3DA0000 {

	kgsl_smmu: kgsl-smmu@3da0000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x3DA0000 0x10000>,

			<0x3DC2000 0x20>;
@@ -30,24 +30,24 @@ 
				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;



		gfx_0_tbu: gfx_0_tbu@0x3DC5000 {

		gfx_0_tbu: gfx_0_tbu@3dc5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x3DC5000 0x1000>,

				<0x3DC2200 0x8>;

			reg-names = "base", "status-reg";

			reg-names = "base", "status";

			qcom,stream-id-range = <0x0 0x400>;

		};



		gfx_1_tbu: gfx_1_tbu@0x3DC9000 {

		gfx_1_tbu: gfx_1_tbu@3dc9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x3DC9000 0x1000>,

				<0x3DC2208 0x8>;

			reg-names = "base", "status-reg";

			reg-names = "base", "status";

			qcom,stream-id-range = <0x400 0x400>;

		};

	};



	apps_smmu: apps-smmu@0x15000000 {

	apps_smmu: apps-smmu@15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x100000>,

			<0x15182000 0x20>;
@@ -158,7 +158,7 @@ 
				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;



		anoc_1_tbu: anoc_1_tbu@0x15185000 {

		anoc_1_tbu: anoc_1_tbu@15185000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15185000 0x1000>,

				<0x15182200 0x8>;
@@ -166,7 +166,7 @@ 
			qcom,stream-id-range = <0x0 0x400>;

		};



		anoc_2_tbu: anoc_2_tbu@0x15189000 {

		anoc_2_tbu: anoc_2_tbu@15189000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15189000 0x1000>,

				<0x15182208 0x8>;
@@ -174,7 +174,7 @@ 
			qcom,stream-id-range = <0x400 0x400>;

		};



		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 {

		mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1518D000 0x1000>,

				<0x15182210 0x8>;
@@ -182,7 +182,7 @@ 
			qcom,stream-id-range = <0x800 0x400>;

		};



		mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 {

		mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15191000 0x1000>,

				<0x15182218 0x8>;
@@ -191,7 +191,7 @@ 


		};



		compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 {

		compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15195000 0x1000>,

				<0x15182220 0x8>;
@@ -199,7 +199,7 @@ 
			qcom,stream-id-range = <0x1000 0x400>;

		};



		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {

		compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15199000 0x1000>,

				<0x15182228 0x8>;
@@ -207,7 +207,7 @@ 
			qcom,stream-id-range = <0x1400 0x400>;

		};



		adsp_tbu: adsp_tbu@0x1519D000 {

		adsp_tbu: adsp_tbu@1519d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1519D000 0x1000>,

				<0x15182230 0x8>;
@@ -215,7 +215,7 @@ 
			qcom,stream-id-range = <0x1800 0x400>;

		};



		anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 {

		anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151A1000 0x1000>,

				<0x15182238 0x8>;
@@ -223,7 +223,7 @@ 
			qcom,stream-id-range = <0x1c00 0x400>;

		};



		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151A5000 {

		mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151A5000 0x1000>,

				<0x15182240 0x8>;
@@ -231,7 +231,7 @@ 
			qcom,stream-id-range = <0x2000 0x400>;

		};



		mnoc_sf_1_tbu: mnoc_sf_1_tbu@0x151A9000 {

		mnoc_sf_1_tbu: mnoc_sf_1_tbu@151a9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151A9000 0x1000>,

				<0x15182248 0x8>;