Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c55b2d98 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'xgene-drivers-for-4.9' of https://github.com/AppliedMicro/xgene-next into next/drivers 

Pull "X-Gene driver changes queued for v4.9" from Duc Dang:

This patch set includes:
+ X-Gene SoC Performance Monitoring Unit (PMU) driver

* tag 'xgene-drivers-for-4.9' of https://github.com/AppliedMicro/xgene-next:
  perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
  Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
  MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
parents 7a4c66d0 832c927d

Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt

0 → 100644
+112 −0
Original line number Diff line number Diff line 
* APM X-Gene SoC PMU bindings



This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.

The following PMU devices are supported:



  L3C			- L3 cache controller

  IOB			- IO bridge

  MCB			- Memory controller bridge

  MC			- Memory controller



The following section describes the SoC PMU DT node binding.



Required properties:

- compatible		: Shall be "apm,xgene-pmu" for revision 1 or

                          "apm,xgene-pmu-v2" for revision 2.

- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.

- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.

- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.

- reg			: First resource shall be the CPU bus PMU resource.

- interrupts            : Interrupt-specifier for PMU IRQ.



Required properties for L3C subnode:

- compatible		: Shall be "apm,xgene-pmu-l3c".

- reg			: First resource shall be the L3C PMU resource.



Required properties for IOB subnode:

- compatible		: Shall be "apm,xgene-pmu-iob".

- reg			: First resource shall be the IOB PMU resource.



Required properties for MCB subnode:

- compatible		: Shall be "apm,xgene-pmu-mcb".

- reg			: First resource shall be the MCB PMU resource.

- enable-bit-index	: The bit indicates if the according MCB is enabled.



Required properties for MC subnode:

- compatible		: Shall be "apm,xgene-pmu-mc".

- reg			: First resource shall be the MC PMU resource.

- enable-bit-index	: The bit indicates if the according MC is enabled.



Example:

	csw: csw@7e200000 {

		compatible = "apm,xgene-csw", "syscon";

		reg = <0x0 0x7e200000 0x0 0x1000>;

	};



	mcba: mcba@7e700000 {

		compatible = "apm,xgene-mcb", "syscon";

		reg = <0x0 0x7e700000 0x0 0x1000>;

	};



	mcbb: mcbb@7e720000 {

		compatible = "apm,xgene-mcb", "syscon";

		reg = <0x0 0x7e720000 0x0 0x1000>;

	};



	pmu: pmu@78810000 {

		compatible = "apm,xgene-pmu-v2";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		regmap-csw = <&csw>;

		regmap-mcba = <&mcba>;

		regmap-mcbb = <&mcbb>;

		reg = <0x0 0x78810000 0x0 0x1000>;

		interrupts = <0x0 0x22 0x4>;



		pmul3c@7e610000 {

			compatible = "apm,xgene-pmu-l3c";

			reg = <0x0 0x7e610000 0x0 0x1000>;

		};



		pmuiob@7e940000 {

			compatible = "apm,xgene-pmu-iob";

			reg = <0x0 0x7e940000 0x0 0x1000>;

		};



		pmucmcb@7e710000 {

			compatible = "apm,xgene-pmu-mcb";

			reg = <0x0 0x7e710000 0x0 0x1000>;

			enable-bit-index = <0>;

		};



		pmucmcb@7e730000 {

			compatible = "apm,xgene-pmu-mcb";

			reg = <0x0 0x7e730000 0x0 0x1000>;

			enable-bit-index = <1>;

		};



		pmucmc@7e810000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e810000 0x0 0x1000>;

			enable-bit-index = <0>;

		};



		pmucmc@7e850000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e850000 0x0 0x1000>;

			enable-bit-index = <1>;

		};



		pmucmc@7e890000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e890000 0x0 0x1000>;

			enable-bit-index = <2>;

		};



		pmucmc@7e8d0000 {

			compatible = "apm,xgene-pmu-mc";

			reg = <0x0 0x7e8d0000 0x0 0x1000>;

			enable-bit-index = <3>;

		};

	};

Documentation/perf/xgene-pmu.txt

0 → 100644
+48 −0
Original line number Diff line number Diff line 
APM X-Gene SoC Performance Monitoring Unit (PMU)

================================================



X-Gene SoC PMU consists of various independent system device PMUs such as

L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory

controller(s). These PMU devices are loosely architected to follow the

same model as the PMU for ARM cores. The PMUs share the same top level

interrupt and status CSR region.



PMU (perf) driver

-----------------



The xgene-pmu driver registers several perf PMU drivers. Each of the perf

driver provides description of its available events and configuration options

in sysfs, see /sys/devices/<l3cX/iobX/mcbX/mcX>/.



The "format" directory describes format of the config (event ID),

config1 (agent ID) fields of the perf_event_attr structure. The "events"

directory provides configuration templates for all supported event types that

can be used with perf tool. For example, "l3c0/bank-fifo-full/" is an

equivalent of "l3c0/config=0x0b/".



Most of the SoC PMU has a specific list of agent ID used for monitoring

performance of a specific datapath. For example, agents of a L3 cache can be

a specific CPU or an I/O bridge. Each PMU has a set of 2 registers capable of

masking the agents from which the request come from. If the bit with

the bit number corresponding to the agent is set, the event is counted only if

it is caused by a request from that agent. Each agent ID bit is inversely mapped

to a corresponding bit in "config1" field. By default, the event will be

counted for all agent requests (config1 = 0x0). For all the supported agents of

each PMU, please refer to APM X-Gene User Manual.



Each perf driver also provides a "cpumask" sysfs attribute, which contains a

single CPU ID of the processor which will be used to handle all the PMU events.



Example for perf tool use:



 / # perf list | grep -e l3c -e iob -e mcb -e mc

   l3c0/ackq-full/                                    [Kernel PMU event]

 <...>

   mcb1/mcb-csw-stall/                                [Kernel PMU event]



 / # perf stat -a -e l3c0/read-miss/,mcb1/csw-write-request/ sleep 1



 / # perf stat -a -e l3c0/read-miss,config1=0xfffffffffffffffe/ sleep 1



The driver does not support sampling, therefore "perf record" will

not work. Per-task (without "-a") perf sessions are not supported.

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -856,6 +856,13 @@ F: drivers/net/phy/mdio-xgene.c 
F:	Documentation/devicetree/bindings/net/apm-xgene-enet.txt

F:	Documentation/devicetree/bindings/net/apm-xgene-mdio.txt



APPLIED MICRO (APM) X-GENE SOC PMU

M:	Tai Nguyen <ttnguyen@apm.com>

S:	Supported

F:	drivers/perf/xgene_pmu.c

F:	Documentation/perf/xgene-pmu.txt

F:	Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt



APTINA CAMERA SENSOR PLL

M:	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>

L:	linux-media@vger.kernel.org

drivers/perf/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -12,4 +12,11 @@ config ARM_PMU 
	  Say y if you want to use CPU performance monitors on ARM-based

	  systems.



config XGENE_PMU

        depends on PERF_EVENTS && ARCH_XGENE

        bool "APM X-Gene SoC PMU"

        default n

        help

          Say y if you want to use APM X-Gene SoC performance monitors.



endmenu

drivers/perf/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_ARM_PMU) += arm_pmu.o

obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o