drm/i915/ringbuffer: Handle cliprects in the caller (c4e7a414) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/i915/i915_dma.c

+11 −11

Original line number	Original line	Diff line number	Diff line
	@@ -352,16 +352,16 @@ static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)

	int		int
	i915_emit_box(struct drm_device *dev,		i915_emit_box(struct drm_device *dev,
	struct drm_clip_rect *boxes,		struct drm_clip_rect *box,
	int i, int DR1, int DR4)		int DR1, int DR4)
	{		{
	struct drm_i915_private *dev_priv = dev->dev_private;		struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_clip_rect box = boxes[i];
	int ret;		int ret;

	if (box.y2 <= box.y1 \|\| box.x2 <= box.x1 \|\| box.y2 <= 0 \|\| box.x2 <= 0) {		if (box->y2 <= box->y1 \|\| box->x2 <= box->x1 \|\|
			box->y2 <= 0 \|\| box->x2 <= 0) {
	DRM_ERROR("Bad box %d,%d..%d,%d\n",		DRM_ERROR("Bad box %d,%d..%d,%d\n",
	box.x1, box.y1, box.x2, box.y2);		box->x1, box->y1, box->x2, box->y2);
	return -EINVAL;		return -EINVAL;
	}		}

	@@ -371,8 +371,8 @@ i915_emit_box(struct drm_device *dev,
	return ret;		return ret;

	OUT_RING(GFX_OP_DRAWRECT_INFO_I965);		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
	OUT_RING((box.x1 & 0xffff) \| (box.y1 << 16));		OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
	OUT_RING(((box.x2 - 1) & 0xffff) \| ((box.y2 - 1) << 16));		OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
	OUT_RING(DR4);		OUT_RING(DR4);
	} else {		} else {
	ret = BEGIN_LP_RING(6);		ret = BEGIN_LP_RING(6);
	@@ -381,8 +381,8 @@ i915_emit_box(struct drm_device *dev,

	OUT_RING(GFX_OP_DRAWRECT_INFO);		OUT_RING(GFX_OP_DRAWRECT_INFO);
	OUT_RING(DR1);		OUT_RING(DR1);
	OUT_RING((box.x1 & 0xffff) \| (box.y1 << 16));		OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
	OUT_RING(((box.x2 - 1) & 0xffff) \| ((box.y2 - 1) << 16));		OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
	OUT_RING(DR4);		OUT_RING(DR4);
	OUT_RING(0);		OUT_RING(0);
	}		}
	@@ -434,7 +434,7 @@ static int i915_dispatch_cmdbuffer(struct drm_device * dev,

	for (i = 0; i < count; i++) {		for (i = 0; i < count; i++) {
	if (i < nbox) {		if (i < nbox) {
	ret = i915_emit_box(dev, cliprects, i,		ret = i915_emit_box(dev, &cliprects[i],
	cmd->DR1, cmd->DR4);		cmd->DR1, cmd->DR4);
	if (ret)		if (ret)
	return ret;		return ret;
	@@ -467,7 +467,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
	count = nbox ? nbox : 1;		count = nbox ? nbox : 1;
	for (i = 0; i < count; i++) {		for (i = 0; i < count; i++) {
	if (i < nbox) {		if (i < nbox) {
	ret = i915_emit_box(dev, cliprects, i,		ret = i915_emit_box(dev, &cliprects[i],
	batch->DR1, batch->DR4);		batch->DR1, batch->DR4);
	if (ret)		if (ret)
	return ret;		return ret;

drivers/gpu/drm/i915/i915_drv.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -966,8 +966,8 @@ extern int i915_driver_device_is_agp(struct drm_device * dev);
	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,		extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
	unsigned long arg);		unsigned long arg);
	extern int i915_emit_box(struct drm_device *dev,		extern int i915_emit_box(struct drm_device *dev,
	struct drm_clip_rect *boxes,		struct drm_clip_rect *box,
	int i, int DR1, int DR4);		int DR1, int DR4);
	extern int i915_reset(struct drm_device *dev, u8 flags);		extern int i915_reset(struct drm_device *dev, u8 flags);
	extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);		extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
	extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);		extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+25 −5

Original line number	Original line	Diff line number	Diff line
	@@ -825,6 +825,7 @@ i915_gem_do_execbuffer(struct drm_device dev, void data,
	struct drm_i915_gem_object *batch_obj;		struct drm_i915_gem_object *batch_obj;
	struct drm_clip_rect *cliprects = NULL;		struct drm_clip_rect *cliprects = NULL;
	struct intel_ring_buffer *ring;		struct intel_ring_buffer *ring;
			u32 exec_start, exec_len;
	int ret, i;		int ret, i;

	if (!i915_gem_check_execbuffer(args)) {		if (!i915_gem_check_execbuffer(args)) {
	@@ -871,6 +872,11 @@ i915_gem_do_execbuffer(struct drm_device dev, void data,
	}		}

	if (args->num_cliprects != 0) {		if (args->num_cliprects != 0) {
			if (ring != &dev_priv->render_ring) {
			DRM_ERROR("clip rectangles are only valid with the render ring\n");
			return -EINVAL;
			}

	cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),		cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
	GFP_KERNEL);		GFP_KERNEL);
	if (cliprects == NULL) {		if (cliprects == NULL) {
	@@ -959,11 +965,25 @@ i915_gem_do_execbuffer(struct drm_device dev, void data,
	if (ret)		if (ret)
	goto err;		goto err;

			exec_start = batch_obj->gtt_offset + args->batch_start_offset;
			exec_len = args->batch_len;
			if (cliprects) {
			for (i = 0; i < args->num_cliprects; i++) {
			ret = i915_emit_box(dev, &cliprects[i],
			args->DR1, args->DR4);
			if (ret)
			goto err;

	ret = ring->dispatch_execbuffer(ring,		ret = ring->dispatch_execbuffer(ring,
	args, cliprects,		exec_start, exec_len);
	batch_obj->gtt_offset);
	if (ret)		if (ret)
	goto err;		goto err;
			}
			} else {
			ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
			if (ret)
			goto err;
			}

	i915_gem_execbuffer_move_to_active(&objects, ring);		i915_gem_execbuffer_move_to_active(&objects, ring);
	i915_gem_execbuffer_retire_commands(dev, file, ring);		i915_gem_execbuffer_retire_commands(dev, file, ring);

drivers/gpu/drm/i915/intel_ringbuffer.c

+28 −58

Original line number	Original line	Diff line number	Diff line
	@@ -508,25 +508,18 @@ ring_status_page_get_seqno(struct intel_ring_buffer *ring)
	}		}

	static int		static int
	ring_dispatch_execbuffer(struct intel_ring_buffer *ring,		ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
	struct drm_i915_gem_execbuffer2 *exec,
	struct drm_clip_rect *cliprects,
	uint64_t exec_offset)
	{		{
	uint32_t exec_start;
	int ret;		int ret;

	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;

	ret = intel_ring_begin(ring, 2);		ret = intel_ring_begin(ring, 2);
	if (ret)		if (ret)
	return ret;		return ret;

	intel_ring_emit(ring,		intel_ring_emit(ring,
	MI_BATCH_BUFFER_START \|		MI_BATCH_BUFFER_START \| (2 << 6) \|
	(2 << 6) \|
	MI_BATCH_NON_SECURE_I965);		MI_BATCH_NON_SECURE_I965);
	intel_ring_emit(ring, exec_start);		intel_ring_emit(ring, offset);
	intel_ring_advance(ring);		intel_ring_advance(ring);

	return 0;		return 0;
	@@ -534,38 +527,22 @@ ring_dispatch_execbuffer(struct intel_ring_buffer *ring,

	static int		static int
	render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,		render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
	struct drm_i915_gem_execbuffer2 *exec,		u32 offset, u32 len)
	struct drm_clip_rect *cliprects,
	uint64_t exec_offset)
	{		{
	struct drm_device *dev = ring->dev;		struct drm_device *dev = ring->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;		drm_i915_private_t *dev_priv = dev->dev_private;
	int nbox = exec->num_cliprects;		int ret;
	uint32_t exec_start, exec_len;
	int i, count, ret;

	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
	exec_len = (uint32_t) exec->batch_len;

	trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);		trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);

	count = nbox ? nbox : 1;
	for (i = 0; i < count; i++) {
	if (i < nbox) {
	ret = i915_emit_box(dev, cliprects, i,
	exec->DR1, exec->DR4);
	if (ret)
	return ret;
	}

	if (IS_I830(dev) \|\| IS_845G(dev)) {		if (IS_I830(dev) \|\| IS_845G(dev)) {
	ret = intel_ring_begin(ring, 4);		ret = intel_ring_begin(ring, 4);
	if (ret)		if (ret)
	return ret;		return ret;

	intel_ring_emit(ring, MI_BATCH_BUFFER);		intel_ring_emit(ring, MI_BATCH_BUFFER);
	intel_ring_emit(ring, exec_start \| MI_BATCH_NON_SECURE);		intel_ring_emit(ring, offset \| MI_BATCH_NON_SECURE);
	intel_ring_emit(ring, exec_start + exec_len - 4);		intel_ring_emit(ring, offset + len - 8);
	intel_ring_emit(ring, 0);		intel_ring_emit(ring, 0);
	} else {		} else {
	ret = intel_ring_begin(ring, 2);		ret = intel_ring_begin(ring, 2);
	@@ -574,18 +551,16 @@ render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,

	if (INTEL_INFO(dev)->gen >= 4) {		if (INTEL_INFO(dev)->gen >= 4) {
	intel_ring_emit(ring,		intel_ring_emit(ring,
	MI_BATCH_BUFFER_START \| (2 << 6)		MI_BATCH_BUFFER_START \| (2 << 6) \|
	\| MI_BATCH_NON_SECURE_I965);		MI_BATCH_NON_SECURE_I965);
	intel_ring_emit(ring, exec_start);		intel_ring_emit(ring, offset);
	} else {		} else {
	intel_ring_emit(ring, MI_BATCH_BUFFER_START		intel_ring_emit(ring,
	\| (2 << 6));		MI_BATCH_BUFFER_START \| (2 << 6));
	intel_ring_emit(ring, exec_start \|		intel_ring_emit(ring, offset \| MI_BATCH_NON_SECURE);
	MI_BATCH_NON_SECURE);
	}		}
	}		}
	intel_ring_advance(ring);		intel_ring_advance(ring);
	}

	return 0;		return 0;
	}		}
	@@ -904,22 +879,17 @@ static void gen6_ring_flush(struct intel_ring_buffer *ring,

	static int		static int
	gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,		gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
	struct drm_i915_gem_execbuffer2 *exec,		u32 offset, u32 len)
	struct drm_clip_rect *cliprects,
	uint64_t exec_offset)
	{		{
	uint32_t exec_start;
	int ret;		int ret;

	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;

	ret = intel_ring_begin(ring, 2);		ret = intel_ring_begin(ring, 2);
	if (ret)		if (ret)
	return ret;		return ret;

	intel_ring_emit(ring, MI_BATCH_BUFFER_START \| MI_BATCH_NON_SECURE_I965);		intel_ring_emit(ring, MI_BATCH_BUFFER_START \| MI_BATCH_NON_SECURE_I965);
	/* bit0-7 is the length on GEN6+ */		/* bit0-7 is the length on GEN6+ */
	intel_ring_emit(ring, exec_start);		intel_ring_emit(ring, offset);
	intel_ring_advance(ring);		intel_ring_advance(ring);

	return 0;		return 0;

drivers/gpu/drm/i915/intel_ringbuffer.h

+1 −3

Original line number	Original line	Diff line number	Diff line
	@@ -57,9 +57,7 @@ struct intel_ring_buffer {
	u32 *seqno);		u32 *seqno);
	u32 (get_seqno)(struct intel_ring_buffer ring);		u32 (get_seqno)(struct intel_ring_buffer ring);
	int (dispatch_execbuffer)(struct intel_ring_buffer ring,		int (dispatch_execbuffer)(struct intel_ring_buffer ring,
	struct drm_i915_gem_execbuffer2 *exec,		u32 offset, u32 length);
	struct drm_clip_rect *cliprects,
	uint64_t exec_offset);
	void (cleanup)(struct intel_ring_buffer ring);		void (cleanup)(struct intel_ring_buffer ring);

	/**		/**