Loading drivers/gpu/drm/i915/i915_drv.h +0 −1 Original line number Diff line number Diff line Loading @@ -3350,7 +3350,6 @@ extern void intel_set_rps(struct drm_device *dev, u8 val); extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); extern void intel_detect_pch(struct drm_device *dev); extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); extern int intel_enable_rc6(const struct drm_device *dev); extern bool i915_semaphore_is_enabled(struct drm_device *dev); Loading drivers/gpu/drm/i915/intel_display.c +19 −3 Original line number Diff line number Diff line Loading @@ -4078,6 +4078,22 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) } } /* Return which DP Port should be selected for Transcoder DP control */ static enum port intel_trans_dp_port_sel(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct intel_encoder *encoder; for_each_encoder_on_crtc(dev, crtc, encoder) { if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || encoder->type == INTEL_OUTPUT_EDP) return enc_to_dig_port(&encoder->base)->port; } return -1; } /* * Enable PCH resources required for PCH ports: * - PCH PLLs Loading Loading @@ -4156,13 +4172,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; switch (intel_trans_dp_port_sel(crtc)) { case PCH_DP_B: case PORT_B: temp |= TRANS_DP_PORT_SEL_B; break; case PCH_DP_C: case PORT_C: temp |= TRANS_DP_PORT_SEL_C; break; case PCH_DP_D: case PORT_D: temp |= TRANS_DP_PORT_SEL_D; break; default: Loading drivers/gpu/drm/i915/intel_dp.c +0 −19 Original line number Diff line number Diff line Loading @@ -5063,25 +5063,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) return ret; } /* Return which DP Port should be selected for Transcoder DP control */ int intel_trans_dp_port_sel(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct intel_encoder *intel_encoder; struct intel_dp *intel_dp; for_each_encoder_on_crtc(dev, crtc, intel_encoder) { intel_dp = enc_to_intel_dp(&intel_encoder->base); if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) return intel_dp->output_reg; } return -1; } /* check the VBT to see whether the eDP is on another port */ bool intel_dp_is_edp(struct drm_device *dev, enum port port) { Loading Loading
drivers/gpu/drm/i915/i915_drv.h +0 −1 Original line number Diff line number Diff line Loading @@ -3350,7 +3350,6 @@ extern void intel_set_rps(struct drm_device *dev, u8 val); extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); extern void intel_detect_pch(struct drm_device *dev); extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); extern int intel_enable_rc6(const struct drm_device *dev); extern bool i915_semaphore_is_enabled(struct drm_device *dev); Loading
drivers/gpu/drm/i915/intel_display.c +19 −3 Original line number Diff line number Diff line Loading @@ -4078,6 +4078,22 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) } } /* Return which DP Port should be selected for Transcoder DP control */ static enum port intel_trans_dp_port_sel(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct intel_encoder *encoder; for_each_encoder_on_crtc(dev, crtc, encoder) { if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || encoder->type == INTEL_OUTPUT_EDP) return enc_to_dig_port(&encoder->base)->port; } return -1; } /* * Enable PCH resources required for PCH ports: * - PCH PLLs Loading Loading @@ -4156,13 +4172,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; switch (intel_trans_dp_port_sel(crtc)) { case PCH_DP_B: case PORT_B: temp |= TRANS_DP_PORT_SEL_B; break; case PCH_DP_C: case PORT_C: temp |= TRANS_DP_PORT_SEL_C; break; case PCH_DP_D: case PORT_D: temp |= TRANS_DP_PORT_SEL_D; break; default: Loading
drivers/gpu/drm/i915/intel_dp.c +0 −19 Original line number Diff line number Diff line Loading @@ -5063,25 +5063,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) return ret; } /* Return which DP Port should be selected for Transcoder DP control */ int intel_trans_dp_port_sel(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct intel_encoder *intel_encoder; struct intel_dp *intel_dp; for_each_encoder_on_crtc(dev, crtc, intel_encoder) { intel_dp = enc_to_intel_dp(&intel_encoder->base); if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) return intel_dp->output_reg; } return -1; } /* check the VBT to see whether the eDP is on another port */ bool intel_dp_is_edp(struct drm_device *dev, enum port port) { Loading