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Commit c4629c34 authored by Sean Wang's avatar Sean Wang Committed by Matthias Brugger
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arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file 



add basic nodes into the mt7622.dtsi for the system
bring-up which includes ARM CPU, GIC, timer, MediaTek
UART, SYSIRQ and one reserved memory region for ATF.

Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 5771a8c0

arch/arm64/boot/dts/mediatek/mt7622.dtsi

0 → 100644
+110 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 MediaTek Inc.

 * Author: Ming Huang <ming.huang@mediatek.com>

 *	   Sean Wang <sean.wang@mediatek.com>

 *

 * SPDX-License-Identifier: (GPL-2.0 OR MIT)

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "mediatek,mt7622";

	interrupt-parent = <&sysirq>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			clock-frequency = <1300000000>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			clock-frequency = <1300000000>;

		};

	};



	uart_clk: dummy25m {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <25000000>;

	};



	bus_clk: dummy280m {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <280000000>;

	};



	psci {

		compatible  = "arm,psci-0.2";

		method      = "smc";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */

		secmon_reserved: secmon@43000000 {

			reg = <0 0x43000000 0 0x30000>;

			no-map;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

			      IRQ_TYPE_LEVEL_HIGH)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |

			      IRQ_TYPE_LEVEL_HIGH)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |

			      IRQ_TYPE_LEVEL_HIGH)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |

			      IRQ_TYPE_LEVEL_HIGH)>;

	};



	sysirq: interrupt-controller@10200620 {

		compatible = "mediatek,mt7622-sysirq",

			     "mediatek,mt6577-sysirq";

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

		reg = <0 0x10200620 0 0x20>;

	};



	gic: interrupt-controller@10300000 {

		compatible = "arm,gic-400";

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

		reg = <0 0x10310000 0 0x1000>,

		      <0 0x10320000 0 0x1000>,

		      <0 0x10340000 0 0x2000>,

		      <0 0x10360000 0 0x2000>;

	};



	uart0: serial@11002000 {

		compatible = "mediatek,mt7622-uart",

			     "mediatek,mt6577-uart";

		reg = <0 0x11002000 0 0x400>;

		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&uart_clk>, <&bus_clk>;

		clock-names = "baud", "bus";

		status = "disabled";

	};

};