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Commit c3b1feb0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "This is the first round of MIPS fixes for 4.6:

   - Fix spelling mistakes all over arch/mips
   - Provide __bswapsi2 so XZ kernel compression will build with older GCC
   - ATH79 clock fixes.
   - Fix clock-rated copy-paste erros in ATH79 DTS.
   - Fix gisb-arb compatible string for 7435 BMIPS
   - Enable NAND and UBIFS support in CI20.
   - Fix BUG() assertion caused by inapropriate smp_processor_id() use.
   - Fix exception handling issues for the sake of debuggers
   - Fix the last remaining instance of irq_to_gpio in the db1xxx_ss PCMCIA code
   - Fix MSA unaligned load failures
   - Panic if kernel is configured for a not TLB-supported page size
   - Bail out on unsupported relocs in modules.
   - Partial fix for Qemu breakage after recent IPI rewrite
   - Wire up the preadv2 and pwrite2 syscalls
   - Fix the ar724x clock calculation"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: traps.c: Verify the ISA for microMIPS RDHWR emulation
  MIPS: BMIPS: Fix gisb-arb compatible string for 7435
  MIPS: Bail on unsupported module relocs
  MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: use "ref" for reference clock name
  MIPS: ath79: Fix the ar913x reference clock rate
  MIPS: ath79: Fix the ar724x clock calculation
  dt-bindings: clock: qca,ath79-pll: fix copy-paste typos
  MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp'
  FIRMWARE: Broadcom: Fix grammar of warning messages in bcm47xx_sprom.c.
  MIPS: ci20: Enable NAND and UBIFS support in defconfig.
  MIPS: Fix misspellings in comments.
  MIPS: tlb-r4k: panic if the MMU doesn't support PAGE_SIZE
  MIPS: zboot: Remove copied source files on clean
  MIPS: zboot: Fix the build with XZ compression on older GCC versions
  MIPS: Wire up preadv2 and pwrite2 syscalls.
  MIPS: cpu_name_string: Use raw_smp_processor_id().
  pcmcia: db1xxx_ss: fix last irq_to_gpio user
  MIPS: Fix MSA ld unaligned failure cases
  MIPS: Fix broken malta qemu
parents 93e2aeac 3d50a7fb

Documentation/devicetree/bindings/clock/qca,ath79-pll.txt

+3 −3
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller 
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.



Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following

- compatible: has to be "qca,<soctype>-pll" and one of the following

  fallbacks:

  - "qca,ar7100-pll"

  - "qca,ar7240-pll"
@@ -21,8 +21,8 @@ Optional properties: 


Example:



	memory-controller@18050000 {

		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";

	pll-controller@18050000 {

		compatible = "qca,ar9132-pll", "qca,ar9130-pll";

		reg = <0x18050000 0x20>;



		clock-names = "ref";

arch/mips/alchemy/common/dbdma.c

+2 −2
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 
	au1x_dma_chan_t *cp;



	/*

	 * We do the intialization on the first channel allocation.

	 * We do the initialization on the first channel allocation.

	 * We have to wait because of the interrupt handler initialization

	 * which can't be done successfully during board set up.

	 */
@@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) 
	dp->dscr_source1 = dscr->dscr_source1;

	dp->dscr_cmd1 = dscr->dscr_cmd1;

	nbytes = dscr->dscr_cmd1;

	/* Allow the caller to specifiy if an interrupt is generated */

	/* Allow the caller to specify if an interrupt is generated */

	dp->dscr_cmd0 &= ~DSCR_CMD0_IE;

	dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;

	ctp->chan_ptr->ddma_dbell = 0;

arch/mips/alchemy/devboards/db1000.c

+8 −10
Original line number Diff line number Diff line
@@ -503,15 +503,15 @@ int __init db1000_dev_setup(void) 
	if (board == BCSR_WHOAMI_DB1500) {

		c0 = AU1500_GPIO2_INT;

		c1 = AU1500_GPIO5_INT;

		d0 = AU1500_GPIO0_INT;

		d1 = AU1500_GPIO3_INT;

		d0 = 0;	/* GPIO number, NOT irq! */

		d1 = 3; /* GPIO number, NOT irq! */

		s0 = AU1500_GPIO1_INT;

		s1 = AU1500_GPIO4_INT;

	} else if (board == BCSR_WHOAMI_DB1100) {

		c0 = AU1100_GPIO2_INT;

		c1 = AU1100_GPIO5_INT;

		d0 = AU1100_GPIO0_INT;

		d1 = AU1100_GPIO3_INT;

		d0 = 0; /* GPIO number, NOT irq! */

		d1 = 3; /* GPIO number, NOT irq! */

		s0 = AU1100_GPIO1_INT;

		s1 = AU1100_GPIO4_INT;
@@ -545,15 +545,15 @@ int __init db1000_dev_setup(void) 
	} else if (board == BCSR_WHOAMI_DB1000) {

		c0 = AU1000_GPIO2_INT;

		c1 = AU1000_GPIO5_INT;

		d0 = AU1000_GPIO0_INT;

		d1 = AU1000_GPIO3_INT;

		d0 = 0; /* GPIO number, NOT irq! */

		d1 = 3; /* GPIO number, NOT irq! */

		s0 = AU1000_GPIO1_INT;

		s1 = AU1000_GPIO4_INT;

		platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));

	} else if ((board == BCSR_WHOAMI_PB1500) ||

		   (board == BCSR_WHOAMI_PB1500R2)) {

		c0 = AU1500_GPIO203_INT;

		d0 = AU1500_GPIO201_INT;

		d0 = 1; /* GPIO number, NOT irq! */

		s0 = AU1500_GPIO202_INT;

		twosocks = 0;

		flashsize = 64;
@@ -566,7 +566,7 @@ int __init db1000_dev_setup(void) 
		 */

	} else if (board == BCSR_WHOAMI_PB1100) {

		c0 = AU1100_GPIO11_INT;

		d0 = AU1100_GPIO9_INT;

		d0 = 9; /* GPIO number, NOT irq! */

		s0 = AU1100_GPIO10_INT;

		twosocks = 0;

		flashsize = 64;
@@ -583,7 +583,6 @@ int __init db1000_dev_setup(void) 
	} else

		return 0; /* unknown board, no further dev setup to do */



	irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);

	irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
@@ -597,7 +596,6 @@ int __init db1000_dev_setup(void) 
		c0, d0, /*s0*/0, 0, 0);



	if (twosocks) {

		irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);

		irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);

		irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);

arch/mips/alchemy/devboards/db1550.c

+2 −2
Original line number Diff line number Diff line
@@ -514,7 +514,7 @@ static void __init db1550_devices(void) 
		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,

		AU1000_PCMCIA_IO_PHYS_ADDR,

		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,

		AU1550_GPIO3_INT, AU1550_GPIO0_INT,

		AU1550_GPIO3_INT, 0,

		/*AU1550_GPIO21_INT*/0, 0, 0);



	db1x_register_pcmcia_socket(
@@ -524,7 +524,7 @@ static void __init db1550_devices(void) 
		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,

		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,

		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,

		AU1550_GPIO5_INT, AU1550_GPIO1_INT,

		AU1550_GPIO5_INT, 1,

		/*AU1550_GPIO22_INT*/0, 0, 1);



	platform_device_register(&db1550_nand_dev);

arch/mips/ath79/clock.c

+4 −40
Original line number Diff line number Diff line
@@ -26,8 +26,7 @@ 
#include "common.h"



#define AR71XX_BASE_FREQ	40000000

#define AR724X_BASE_FREQ	5000000

#define AR913X_BASE_FREQ	5000000

#define AR724X_BASE_FREQ	40000000



static struct clk *clks[3];

static struct clk_onecell_data clk_data = {
@@ -103,8 +102,8 @@ static void __init ar724x_clocks_init(void) 
	div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);

	freq = div * ref_rate;



	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);

	freq *= div;

	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;

	freq /= div;



	cpu_rate = freq;
@@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void) 
	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar913x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll;

	u32 freq;

	u32 div;



	ref_rate = AR913X_BASE_FREQ;

	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);



	div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);

	freq = div * ref_rate;



	cpu_rate = freq;



	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;

	ddr_rate = freq / div;



	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;

	ahb_rate = cpu_rate / div;



	ath79_add_sys_clkdev("ref", ref_rate);

	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);

	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);

	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);



	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar933x_clocks_init(void)

{

	unsigned long ref_rate;
@@ -443,10 +409,8 @@ void __init ath79_clocks_init(void) 
{

	if (soc_is_ar71xx())

		ar71xx_clocks_init();

	else if (soc_is_ar724x())

	else if (soc_is_ar724x() || soc_is_ar913x())

		ar724x_clocks_init();

	else if (soc_is_ar913x())

		ar913x_clocks_init();

	else if (soc_is_ar933x())

		ar933x_clocks_init();

	else if (soc_is_ar934x())