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Commit c3630cc4 authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher
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ixgbe: Use length to determine if descriptor is done 



This change makes it so that we use the length of the packet instead of the
DD status bit to determine if a new descriptor is ready to be processed.
The obvious advantage is that it cuts down on reads as we don't really even
need the DD bit if going from a 0 to a non-zero value on size is enough to
inform us that the packet has been completed.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 4f4542bf

drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

+1 −1
Original line number Diff line number Diff line
@@ -1868,7 +1868,7 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 
	tx_ntc = tx_ring->next_to_clean;

	rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);



	while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {

	while (rx_desc->wb.upper.length) {

		/* check Rx buffer */

		rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

+8 −6
Original line number Diff line number Diff line
@@ -1640,8 +1640,8 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 
			i -= rx_ring->count;

		}



		/* clear the status bits for the next_to_use descriptor */

		rx_desc->wb.upper.status_error = 0;

		/* clear the length for the next_to_use descriptor */

		rx_desc->wb.upper.length = 0;



		cleaned_count--;

	} while (cleaned_count);
@@ -2154,7 +2154,7 @@ static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 


		rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);



		if (!rx_desc->wb.upper.status_error)

		if (!rx_desc->wb.upper.length)

			break;



		/* This memory barrier is needed to keep us from reading
@@ -3698,6 +3698,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 
			     struct ixgbe_ring *ring)

{

	struct ixgbe_hw *hw = &adapter->hw;

	union ixgbe_adv_rx_desc *rx_desc;

	u64 rdba = ring->dma;

	u32 rxdctl;

	u8 reg_idx = ring->reg_idx;
@@ -3732,6 +3733,10 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 
		rxdctl |=  0x080420;

	}



	/* initialize Rx descriptor 0 */

	rx_desc = IXGBE_RX_DESC(ring, 0);

	rx_desc->wb.upper.length = 0;



	/* enable receive descriptor ring */

	rxdctl |= IXGBE_RXDCTL_ENABLE;

	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
@@ -4940,9 +4945,6 @@ static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 
	size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;

	memset(rx_ring->rx_buffer_info, 0, size);



	/* Zero out the descriptor ring */

	memset(rx_ring->desc, 0, rx_ring->size);



	rx_ring->next_to_alloc = 0;

	rx_ring->next_to_clean = 0;

	rx_ring->next_to_use = 0;