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Commit c32f3861 authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 



Merge the 'net' tree to get the recent set of netfilter bug fixes in
order to assist with some merge hassles Pablo is going to have to deal
with for upcoming changes.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 761743eb 0dcd5052

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 6

SUBLEVEL = 0

EXTRAVERSION = -rc2

EXTRAVERSION = -rc3

NAME = Saber-toothed Squirrel



# *DOCUMENTATION*

drivers/acpi/acpica/tbxface.c

+1 −0
Original line number Diff line number Diff line
@@ -387,6 +387,7 @@ acpi_get_table_with_size(char *signature, 


	return (AE_NOT_FOUND);

}

ACPI_EXPORT_SYMBOL(acpi_get_table_with_size)



acpi_status

acpi_get_table(char *signature,

drivers/char/agp/intel-agp.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
#define I830_PTE_SYSTEM_CACHED  0x00000006

/* GT PTE cache control fields */

#define GEN6_PTE_UNCACHED	0x00000002

#define HSW_PTE_UNCACHED	0x00000000

#define GEN6_PTE_LLC		0x00000004

#define GEN6_PTE_LLC_MLC	0x00000006

#define GEN6_PTE_GFDT		0x00000008

drivers/char/agp/intel-gtt.c

+69 −36
Original line number Diff line number Diff line
@@ -1156,6 +1156,30 @@ static bool gen6_check_flags(unsigned int flags) 
	return true;

}



static void haswell_write_entry(dma_addr_t addr, unsigned int entry,

				unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	} else { /* set 'normal'/'cached' to LLC by default */

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);

}



static void gen6_write_entry(dma_addr_t addr, unsigned int entry,

			     unsigned int flags)

{
@@ -1382,6 +1406,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { 
	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver haswell_gtt_driver = {

	.gen = 6,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = haswell_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver valleyview_gtt_driver = {

	.gen = 7,

	.setup = i9xx_setup,
@@ -1499,77 +1532,77 @@ static const struct intel_gtt_driver_description { 
	{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,

	    "ValleyView", &valleyview_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	    "Haswell", &haswell_gtt_driver },

	{ 0, NULL, NULL }

};

drivers/gpu/drm/drm_modes.c

+0 −3
Original line number Diff line number Diff line
@@ -706,9 +706,6 @@ void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags) 
	p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);

	p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);

	p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);



	p->crtc_hadjusted = false;

	p->crtc_vadjusted = false;

}

EXPORT_SYMBOL(drm_mode_set_crtcinfo);