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Commit c3168cab authored by Ganesh Goudar's avatar Ganesh Goudar Committed by David S. Miller
Browse files

cxgb4/cxgbvf: Handle 32-bit fw port capabilities 



Implement new 32-bit Firmware Port Capabilities in order to
handle new speeds which couldn't be represented in the old 16-bit
Firmware Port Capabilities values.

Based on the original work of Casey Leedom <leedom@chelsio.com>

Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 274043c6

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

+31 −12
Original line number Diff line number Diff line
@@ -104,13 +104,13 @@ enum dev_state { 
	DEV_STATE_ERR

};



enum {

enum cc_pause {

	PAUSE_RX      = 1 << 0,

	PAUSE_TX      = 1 << 1,

	PAUSE_AUTONEG = 1 << 2

};



enum {

enum cc_fec {

	FEC_AUTO      = 1 << 0,	 /* IEEE 802.3 "automatic" */

	FEC_RS        = 1 << 1,  /* Reed-Solomon */

	FEC_BASER_RS  = 1 << 2   /* BaseR/Reed-Solomon */
@@ -366,6 +366,7 @@ struct adapter_params { 
	unsigned int max_ordird_qp;       /* Max read depth per RDMA QP */

	unsigned int max_ird_adapter;     /* Max read depth per adapter */

	bool fr_nsmr_tpte_wr_support;	  /* FW support for FR_NSMR_TPTE_WR */

	u8 fw_caps_support;		/* 32-bit Port Capabilities */



	/* MPS Buffer Group Map[per Port].  Bit i is set if buffer group i is

	 * used by the Port
@@ -439,18 +440,34 @@ struct trace_params { 
	unsigned char port;

};



/* Firmware Port Capabilities types. */



typedef u16 fw_port_cap16_t;	/* 16-bit Port Capabilities integral value */

typedef u32 fw_port_cap32_t;	/* 32-bit Port Capabilities integral value */



enum fw_caps {

	FW_CAPS_UNKNOWN	= 0,	/* 0'ed out initial state */

	FW_CAPS16	= 1,	/* old Firmware: 16-bit Port Capabilities */

	FW_CAPS32	= 2,	/* new Firmware: 32-bit Port Capabilities */

};



struct link_config {

	unsigned short supported;        /* link capabilities */

	unsigned short advertising;      /* advertised capabilities */

	unsigned short lp_advertising;   /* peer advertised capabilities */

	unsigned int   requested_speed;  /* speed user has requested */

	unsigned int   speed;            /* actual link speed */

	unsigned char  requested_fc;     /* flow control user has requested */

	unsigned char  fc;               /* actual link flow control */

	unsigned char  auto_fec;	 /* Forward Error Correction: */

	unsigned char  requested_fec;	 /* "automatic" (IEEE 802.3), */

	unsigned char  fec;		 /* requested, and actual in use */

	fw_port_cap32_t pcaps;           /* link capabilities */

	fw_port_cap32_t def_acaps;       /* default advertised capabilities */

	fw_port_cap32_t acaps;           /* advertised capabilities */

	fw_port_cap32_t lpacaps;         /* peer advertised capabilities */



	fw_port_cap32_t speed_caps;      /* speed(s) user has requested */

	unsigned int   speed;            /* actual link speed (Mb/s) */



	enum cc_pause  requested_fc;     /* flow control user has requested */

	enum cc_pause  fc;               /* actual link flow control */



	enum cc_fec    requested_fec;	 /* Forward Error Correction: */

	enum cc_fec    fec;		 /* requested and actual in use */



	unsigned char  autoneg;          /* autonegotiating? */



	unsigned char  link_ok;          /* link up? */

	unsigned char  link_down_rc;     /* link down reason */

};
@@ -1580,6 +1597,8 @@ int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 
int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);

void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);

int t4_update_port_info(struct port_info *pi);

int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,

		       unsigned int *speedp, unsigned int *mtup);

int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);

void t4_db_full(struct adapter *adapter);

void t4_db_dropped(struct adapter *adapter);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c

+61 −37
Original line number Diff line number Diff line
@@ -533,17 +533,23 @@ static int from_fw_port_mod_type(enum fw_port_type port_type, 
static unsigned int speed_to_fw_caps(int speed)

{

	if (speed == 100)

		return FW_PORT_CAP_SPEED_100M;

		return FW_PORT_CAP32_SPEED_100M;

	if (speed == 1000)

		return FW_PORT_CAP_SPEED_1G;

		return FW_PORT_CAP32_SPEED_1G;

	if (speed == 10000)

		return FW_PORT_CAP_SPEED_10G;

		return FW_PORT_CAP32_SPEED_10G;

	if (speed == 25000)

		return FW_PORT_CAP_SPEED_25G;

		return FW_PORT_CAP32_SPEED_25G;

	if (speed == 40000)

		return FW_PORT_CAP_SPEED_40G;

		return FW_PORT_CAP32_SPEED_40G;

	if (speed == 50000)

		return FW_PORT_CAP32_SPEED_50G;

	if (speed == 100000)

		return FW_PORT_CAP_SPEED_100G;

		return FW_PORT_CAP32_SPEED_100G;

	if (speed == 200000)

		return FW_PORT_CAP32_SPEED_200G;

	if (speed == 400000)

		return FW_PORT_CAP32_SPEED_400G;

	return 0;

}
@@ -560,12 +566,13 @@ static void fw_caps_to_lmm(enum fw_port_type port_type, 
			   unsigned int fw_caps,

			   unsigned long *link_mode_mask)

{

	#define SET_LMM(__lmm_name) __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name \

					## _BIT, link_mode_mask)

	#define SET_LMM(__lmm_name) \

		__set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \

			  link_mode_mask)



	#define FW_CAPS_TO_LMM(__fw_name, __lmm_name) \

		do { \

			if (fw_caps & FW_PORT_CAP_ ## __fw_name) \

			if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \

				SET_LMM(__lmm_name); \

		} while (0)
@@ -645,7 +652,10 @@ static void fw_caps_to_lmm(enum fw_port_type port_type, 
	case FW_PORT_TYPE_KR4_100G:

	case FW_PORT_TYPE_CR4_QSFP:

		SET_LMM(FIBRE);

		SET_LMM(100000baseCR4_Full);

		FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);

		FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);

		FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);

		FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);

		break;



	default:
@@ -663,8 +673,7 @@ static void fw_caps_to_lmm(enum fw_port_type port_type, 
/**

 *	lmm_to_fw_caps - translate ethtool Link Mode Mask to Firmware

 *	capabilities

 *

 *	@link_mode_mask: ethtool Link Mode Mask

 *	@et_lmm: ethtool Link Mode Mask

 *

 *	Translate ethtool Link Mode Mask into a Firmware Port capabilities

 *	value.
@@ -677,7 +686,7 @@ static unsigned int lmm_to_fw_caps(const unsigned long *link_mode_mask) 
		do { \

			if (test_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \

				     link_mode_mask)) \

				fw_caps |= FW_PORT_CAP_ ## __fw_name; \

				fw_caps |= FW_PORT_CAP32_ ## __fw_name; \

		} while (0)



	LMM_TO_FW_CAPS(100baseT_Full, SPEED_100M);
@@ -685,6 +694,7 @@ static unsigned int lmm_to_fw_caps(const unsigned long *link_mode_mask) 
	LMM_TO_FW_CAPS(10000baseT_Full, SPEED_10G);

	LMM_TO_FW_CAPS(40000baseSR4_Full, SPEED_40G);

	LMM_TO_FW_CAPS(25000baseCR_Full, SPEED_25G);

	LMM_TO_FW_CAPS(50000baseCR2_Full, SPEED_50G);

	LMM_TO_FW_CAPS(100000baseCR4_Full, SPEED_100G);



	#undef LMM_TO_FW_CAPS
@@ -698,10 +708,6 @@ static int get_link_ksettings(struct net_device *dev, 
	struct port_info *pi = netdev_priv(dev);

	struct ethtool_link_settings *base = &link_ksettings->base;



	ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);

	ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);

	ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);



	/* For the nonce, the Firmware doesn't send up Port State changes

	 * when the Virtual Interface attached to the Port is down.  So

	 * if it's down, let's grab any changes.
@@ -709,6 +715,10 @@ static int get_link_ksettings(struct net_device *dev, 
	if (!netif_running(dev))

		(void)t4_update_port_info(pi);



	ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);

	ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);

	ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);



	base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type);



	if (pi->mdio_addr >= 0) {
@@ -721,11 +731,11 @@ static int get_link_ksettings(struct net_device *dev, 
		base->mdio_support = 0;

	}



	fw_caps_to_lmm(pi->port_type, pi->link_cfg.supported,

	fw_caps_to_lmm(pi->port_type, pi->link_cfg.pcaps,

		       link_ksettings->link_modes.supported);

	fw_caps_to_lmm(pi->port_type, pi->link_cfg.advertising,

	fw_caps_to_lmm(pi->port_type, pi->link_cfg.acaps,

		       link_ksettings->link_modes.advertising);

	fw_caps_to_lmm(pi->port_type, pi->link_cfg.lp_advertising,

	fw_caps_to_lmm(pi->port_type, pi->link_cfg.lpacaps,

		       link_ksettings->link_modes.lp_advertising);



	if (netif_carrier_ok(dev)) {
@@ -736,8 +746,24 @@ static int get_link_ksettings(struct net_device *dev, 
		base->duplex = DUPLEX_UNKNOWN;

	}



	if (pi->link_cfg.fc & PAUSE_RX) {

		if (pi->link_cfg.fc & PAUSE_TX) {

			ethtool_link_ksettings_add_link_mode(link_ksettings,

							     advertising,

							     Pause);

		} else {

			ethtool_link_ksettings_add_link_mode(link_ksettings,

							     advertising,

							     Asym_Pause);

		}

	} else if (pi->link_cfg.fc & PAUSE_TX) {

		ethtool_link_ksettings_add_link_mode(link_ksettings,

						     advertising,

						     Asym_Pause);

	}



	base->autoneg = pi->link_cfg.autoneg;

	if (pi->link_cfg.supported & FW_PORT_CAP_ANEG)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)

		ethtool_link_ksettings_add_link_mode(link_ksettings,

						     supported, Autoneg);

	if (pi->link_cfg.autoneg)
@@ -748,8 +774,7 @@ static int get_link_ksettings(struct net_device *dev, 
}



static int set_link_ksettings(struct net_device *dev,

			      const struct ethtool_link_ksettings

						*link_ksettings)

			    const struct ethtool_link_ksettings *link_ksettings)

{

	struct port_info *pi = netdev_priv(dev);

	struct link_config *lc = &pi->link_cfg;
@@ -762,12 +787,12 @@ static int set_link_ksettings(struct net_device *dev, 
	if (base->duplex != DUPLEX_FULL)

		return -EINVAL;



	if (!(lc->supported & FW_PORT_CAP_ANEG)) {

	if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {

		/* PHY offers a single speed.  See if that's what's

		 * being requested.

		 */

		if (base->autoneg == AUTONEG_DISABLE &&

		    (lc->supported & speed_to_fw_caps(base->speed)))

		    (lc->pcaps & speed_to_fw_caps(base->speed)))

			return 0;

		return -EINVAL;

	}
@@ -776,18 +801,17 @@ static int set_link_ksettings(struct net_device *dev, 
	if (base->autoneg == AUTONEG_DISABLE) {

		fw_caps = speed_to_fw_caps(base->speed);



		if (!(lc->supported & fw_caps))

		if (!(lc->pcaps & fw_caps))

			return -EINVAL;

		lc->requested_speed = fw_caps;

		lc->advertising = 0;

		lc->speed_caps = fw_caps;

		lc->acaps = 0;

	} else {

		fw_caps =

			 lmm_to_fw_caps(link_ksettings->link_modes.advertising);



		if (!(lc->supported & fw_caps))

		if (!(lc->pcaps & fw_caps))

			return -EINVAL;

		lc->requested_speed = 0;

		lc->advertising = fw_caps | FW_PORT_CAP_ANEG;

		lc->speed_caps = 0;

		lc->acaps = fw_caps | FW_PORT_CAP32_ANEG;

	}

	lc->autoneg = base->autoneg;
@@ -806,9 +830,9 @@ static inline unsigned int fwcap_to_eth_fec(unsigned int fw_fec) 
{

	unsigned int eth_fec = 0;



	if (fw_fec & FW_PORT_CAP_FEC_RS)

	if (fw_fec & FW_PORT_CAP32_FEC_RS)

		eth_fec |= ETHTOOL_FEC_RS;

	if (fw_fec & FW_PORT_CAP_FEC_BASER_RS)

	if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)

		eth_fec |= ETHTOOL_FEC_BASER;



	/* if nothing is set, then FEC is off */
@@ -864,7 +888,7 @@ static int get_fecparam(struct net_device *dev, struct ethtool_fecparam *fec) 
	 * always support IEEE 802.3 "automatic" selection of Link FEC type if

	 * any FEC is supported.

	 */

	fec->fec = fwcap_to_eth_fec(lc->supported);

	fec->fec = fwcap_to_eth_fec(lc->pcaps);

	if (fec->fec != ETHTOOL_FEC_OFF)

		fec->fec |= ETHTOOL_FEC_AUTO;
@@ -917,7 +941,7 @@ static int set_pauseparam(struct net_device *dev, 


	if (epause->autoneg == AUTONEG_DISABLE)

		lc->requested_fc = 0;

	else if (lc->supported & FW_PORT_CAP_ANEG)

	else if (lc->pcaps & FW_PORT_CAP32_ANEG)

		lc->requested_fc = PAUSE_AUTONEG;

	else

		return -EINVAL;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+40 −48
Original line number Diff line number Diff line
@@ -530,13 +530,20 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 
			FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));



		if (cmd == FW_PORT_CMD &&

		    action == FW_PORT_ACTION_GET_PORT_INFO) {

		    (action == FW_PORT_ACTION_GET_PORT_INFO ||

		     action == FW_PORT_ACTION_GET_PORT_INFO32)) {

			int port = FW_PORT_CMD_PORTID_G(

					be32_to_cpu(pcmd->op_to_portid));

			struct net_device *dev =

				q->adap->port[q->adap->chan_map[port]];

			int state_input = ((pcmd->u.info.dcbxdis_pkd &

			struct net_device *dev;

			int dcbxdis, state_input;



			dev = q->adap->port[q->adap->chan_map[port]];

			dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO

				   ? !!(pcmd->u.info.dcbxdis_pkd &

					FW_PORT_CMD_DCBXDIS_F)

				   : !!(pcmd->u.info32.lstatus32_to_cbllen32 &

					FW_PORT_CMD_DCBXDIS32_F));

			state_input = (dcbxdis

				       ? CXGB4_DCB_INPUT_FW_DISABLED

				       : CXGB4_DCB_INPUT_FW_ENABLED);
@@ -2672,11 +2679,10 @@ static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 
{

	struct port_info *pi = netdev_priv(dev);

	struct adapter *adap = pi->adapter;

	struct fw_port_cmd port_cmd, port_rpl;

	u32 link_status, speed = 0;

	unsigned int link_ok, speed, mtu;

	u32 fw_pfvf, fw_class;

	int class_id = vf;

	int link_ok, ret;

	int ret;

	u16 pktsize;



	if (vf >= adap->num_vfs)
@@ -2688,41 +2694,18 @@ static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 
			min_tx_rate, vf);

		return -EINVAL;

	}

	/* Retrieve link details for VF port */

	memset(&port_cmd, 0, sizeof(port_cmd));

	port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |

					    FW_CMD_REQUEST_F |

					    FW_CMD_READ_F |

					    FW_PORT_CMD_PORTID_V(pi->port_id));

	port_cmd.action_to_len16 =

		cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |

			    FW_LEN16(port_cmd));

	ret = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),

			 &port_rpl);



	ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);

	if (ret != FW_SUCCESS) {

		dev_err(adap->pdev_dev,

			"Failed to get link status for VF %d\n", vf);

			"Failed to get link information for VF %d\n", vf);

		return -EINVAL;

	}

	link_status = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype);

	link_ok = (link_status & FW_PORT_CMD_LSTATUS_F) != 0;



	if (!link_ok) {

		dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);

		return -EINVAL;

	}

	/* Determine link speed */

	if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))

		speed = 100;

	else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))

		speed = 1000;

	else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))

		speed = 10000;

	else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))

		speed = 25000;

	else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))

		speed = 40000;

	else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))

		speed = 100000;



	if (max_tx_rate > speed) {

		dev_err(adap->pdev_dev,
@@ -2730,7 +2713,8 @@ static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 
			max_tx_rate, vf, speed);

		return -EINVAL;

	}

	pktsize = be16_to_cpu(port_rpl.u.info.mtu);



	pktsize = mtu;

	/* subtract ethhdr size and 4 bytes crc since, f/w appends it */

	pktsize = pktsize - sizeof(struct ethhdr) - 4;

	/* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
@@ -2741,7 +2725,7 @@ static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 
			      SCHED_CLASS_MODE_CLASS,

			      SCHED_CLASS_RATEUNIT_BITS,

			      SCHED_CLASS_RATEMODE_ABS,

			      pi->port_id, class_id, 0,

			      pi->tx_chan, class_id, 0,

			      max_tx_rate * 1000, 0, pktsize);

	if (ret) {

		dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
@@ -4208,8 +4192,9 @@ static inline bool is_x_10g_port(const struct link_config *lc) 
{

	unsigned int speeds, high_speeds;



	speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));

	high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);

	speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));

	high_speeds = speeds &

			~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);



	return high_speeds != 0;

}
@@ -4590,18 +4575,24 @@ static void print_port_info(const struct net_device *dev) 
	else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)

		spd = " 8 GT/s";



	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)

		bufp += sprintf(bufp, "100M/");

	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)

		bufp += sprintf(bufp, "1G/");

	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)

		bufp += sprintf(bufp, "10G/");

	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)

		bufp += sprintf(bufp, "25G/");

	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)

		bufp += sprintf(bufp, "40G/");

	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)

		bufp += sprintf(bufp, "50G/");

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)

		bufp += sprintf(bufp, "100G/");

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)

		bufp += sprintf(bufp, "200G/");

	if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)

		bufp += sprintf(bufp, "400G/");

	if (bufp != buf)

		--bufp;

	sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
@@ -4707,10 +4698,11 @@ static int config_mgmt_dev(struct pci_dev *pdev) 


	pi = netdev_priv(netdev);

	pi->adapter = adap;

	pi->port_id = adap->pf % adap->params.nports;

	pi->tx_chan = adap->pf % adap->params.nports;

	SET_NETDEV_DEV(netdev, &pdev->dev);



	adap->port[0] = netdev;

	pi->port_id = 0;



	err = register_netdev(adap->port[0]);

	if (err) {

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+453 −127

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

+174 −1
Original line number Diff line number Diff line
@@ -1173,7 +1173,8 @@ enum fw_params_param_pfvf { 
	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,

	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,

	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,

	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32

	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32,

	FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,

};



/*
@@ -2256,6 +2257,7 @@ struct fw_acl_vlan_cmd { 
#define FW_ACL_VLAN_CMD_FM_S	6

#define FW_ACL_VLAN_CMD_FM_V(x)	((x) << FW_ACL_VLAN_CMD_FM_S)



/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */

enum fw_port_cap {

	FW_PORT_CAP_SPEED_100M		= 0x0001,

	FW_PORT_CAP_SPEED_1G		= 0x0002,
@@ -2291,6 +2293,84 @@ enum fw_port_mdi { 
#define FW_PORT_CAP_MDI_S 9

#define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)



/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */

#define	FW_PORT_CAP32_SPEED_100M	0x00000001UL

#define	FW_PORT_CAP32_SPEED_1G		0x00000002UL

#define	FW_PORT_CAP32_SPEED_10G		0x00000004UL

#define	FW_PORT_CAP32_SPEED_25G		0x00000008UL

#define	FW_PORT_CAP32_SPEED_40G		0x00000010UL

#define	FW_PORT_CAP32_SPEED_50G		0x00000020UL

#define	FW_PORT_CAP32_SPEED_100G	0x00000040UL

#define	FW_PORT_CAP32_SPEED_200G	0x00000080UL

#define	FW_PORT_CAP32_SPEED_400G	0x00000100UL

#define	FW_PORT_CAP32_SPEED_RESERVED1	0x00000200UL

#define	FW_PORT_CAP32_SPEED_RESERVED2	0x00000400UL

#define	FW_PORT_CAP32_SPEED_RESERVED3	0x00000800UL

#define	FW_PORT_CAP32_RESERVED1		0x0000f000UL

#define	FW_PORT_CAP32_FC_RX		0x00010000UL

#define	FW_PORT_CAP32_FC_TX		0x00020000UL

#define	FW_PORT_CAP32_802_3_PAUSE	0x00040000UL

#define	FW_PORT_CAP32_802_3_ASM_DIR	0x00080000UL

#define	FW_PORT_CAP32_ANEG		0x00100000UL

#define	FW_PORT_CAP32_MDIX		0x00200000UL

#define	FW_PORT_CAP32_MDIAUTO		0x00400000UL

#define	FW_PORT_CAP32_FEC_RS		0x00800000UL

#define	FW_PORT_CAP32_FEC_BASER_RS	0x01000000UL

#define	FW_PORT_CAP32_FEC_RESERVED1	0x02000000UL

#define	FW_PORT_CAP32_FEC_RESERVED2	0x04000000UL

#define	FW_PORT_CAP32_FEC_RESERVED3	0x08000000UL

#define	FW_PORT_CAP32_RESERVED2		0xf0000000UL



#define FW_PORT_CAP32_SPEED_S	0

#define FW_PORT_CAP32_SPEED_M	0xfff

#define FW_PORT_CAP32_SPEED_V(x)	((x) << FW_PORT_CAP32_SPEED_S)

#define FW_PORT_CAP32_SPEED_G(x) \

	(((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)



#define FW_PORT_CAP32_FC_S	16

#define FW_PORT_CAP32_FC_M	0x3

#define FW_PORT_CAP32_FC_V(x)	((x) << FW_PORT_CAP32_FC_S)

#define FW_PORT_CAP32_FC_G(x) \

	(((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)



#define FW_PORT_CAP32_802_3_S	18

#define FW_PORT_CAP32_802_3_M	0x3

#define FW_PORT_CAP32_802_3_V(x)	((x) << FW_PORT_CAP32_802_3_S)

#define FW_PORT_CAP32_802_3_G(x) \

	(((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)



#define FW_PORT_CAP32_ANEG_S	20

#define FW_PORT_CAP32_ANEG_M	0x1

#define FW_PORT_CAP32_ANEG_V(x)	((x) << FW_PORT_CAP32_ANEG_S)

#define FW_PORT_CAP32_ANEG_G(x) \

	(((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)



enum fw_port_mdi32 {

	FW_PORT_CAP32_MDI_UNCHANGED,

	FW_PORT_CAP32_MDI_AUTO,

	FW_PORT_CAP32_MDI_F_STRAIGHT,

	FW_PORT_CAP32_MDI_F_CROSSOVER

};



#define FW_PORT_CAP32_MDI_S 21

#define FW_PORT_CAP32_MDI_M 3

#define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)

#define FW_PORT_CAP32_MDI_G(x) \

	(((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)



#define FW_PORT_CAP32_FEC_S	23

#define FW_PORT_CAP32_FEC_M	0x1f

#define FW_PORT_CAP32_FEC_V(x)	((x) << FW_PORT_CAP32_FEC_S)

#define FW_PORT_CAP32_FEC_G(x) \

	(((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)



/* macros to isolate various 32-bit Port Capabilities sub-fields */

#define CAP32_SPEED(__cap32) \

	(FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)



#define CAP32_FEC(__cap32) \

	(FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)



enum fw_port_action {

	FW_PORT_ACTION_L1_CFG		= 0x0001,

	FW_PORT_ACTION_L2_CFG		= 0x0002,
@@ -2300,6 +2380,8 @@ enum fw_port_action { 
	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,

	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,

	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,

	FW_PORT_ACTION_L1_CFG32		= 0x0009,

	FW_PORT_ACTION_GET_PORT_INFO32	= 0x000a,

	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,

	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,

	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
@@ -2447,6 +2529,18 @@ struct fw_port_cmd { 
				__be64 r12;

			} control;

		} dcb;

		struct fw_port_l1cfg32 {

			__be32 rcap32;

			__be32 r;

		} l1cfg32;

		struct fw_port_info32 {

			__be32 lstatus32_to_cbllen32;

			__be32 auxlinfo32_mtu32;

			__be32 linkattr32;

			__be32 pcaps32;

			__be32 acaps32;

			__be32 lpacaps32;

		} info32;

	} u;

};
@@ -2555,6 +2649,85 @@ struct fw_port_cmd { 
#define FW_PORT_CMD_DCB_VERSION_G(x)	\

	(((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)



#define FW_PORT_CMD_LSTATUS32_S		31

#define FW_PORT_CMD_LSTATUS32_M		0x1

#define FW_PORT_CMD_LSTATUS32_V(x)	((x) << FW_PORT_CMD_LSTATUS32_S)

#define FW_PORT_CMD_LSTATUS32_G(x)	\

	(((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)

#define FW_PORT_CMD_LSTATUS32_F	FW_PORT_CMD_LSTATUS32_V(1U)



#define FW_PORT_CMD_LINKDNRC32_S	28

#define FW_PORT_CMD_LINKDNRC32_M	0x7

#define FW_PORT_CMD_LINKDNRC32_V(x)	((x) << FW_PORT_CMD_LINKDNRC32_S)

#define FW_PORT_CMD_LINKDNRC32_G(x)	\

	(((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)



#define FW_PORT_CMD_DCBXDIS32_S		27

#define FW_PORT_CMD_DCBXDIS32_M		0x1

#define FW_PORT_CMD_DCBXDIS32_V(x)	((x) << FW_PORT_CMD_DCBXDIS32_S)

#define FW_PORT_CMD_DCBXDIS32_G(x)	\

	(((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)

#define FW_PORT_CMD_DCBXDIS32_F	FW_PORT_CMD_DCBXDIS32_V(1U)



#define FW_PORT_CMD_MDIOCAP32_S		26

#define FW_PORT_CMD_MDIOCAP32_M		0x1

#define FW_PORT_CMD_MDIOCAP32_V(x)	((x) << FW_PORT_CMD_MDIOCAP32_S)

#define FW_PORT_CMD_MDIOCAP32_G(x)	\

	(((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)

#define FW_PORT_CMD_MDIOCAP32_F	FW_PORT_CMD_MDIOCAP32_V(1U)



#define FW_PORT_CMD_MDIOADDR32_S	21

#define FW_PORT_CMD_MDIOADDR32_M	0x1f

#define FW_PORT_CMD_MDIOADDR32_V(x)	((x) << FW_PORT_CMD_MDIOADDR32_S)

#define FW_PORT_CMD_MDIOADDR32_G(x)	\

	(((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)



#define FW_PORT_CMD_PORTTYPE32_S	13

#define FW_PORT_CMD_PORTTYPE32_M	0xff

#define FW_PORT_CMD_PORTTYPE32_V(x)	((x) << FW_PORT_CMD_PORTTYPE32_S)

#define FW_PORT_CMD_PORTTYPE32_G(x)	\

	(((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)



#define FW_PORT_CMD_MODTYPE32_S		8

#define FW_PORT_CMD_MODTYPE32_M		0x1f

#define FW_PORT_CMD_MODTYPE32_V(x)	((x) << FW_PORT_CMD_MODTYPE32_S)

#define FW_PORT_CMD_MODTYPE32_G(x)	\

	(((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)



#define FW_PORT_CMD_CBLLEN32_S		0

#define FW_PORT_CMD_CBLLEN32_M		0xff

#define FW_PORT_CMD_CBLLEN32_V(x)	((x) << FW_PORT_CMD_CBLLEN32_S)

#define FW_PORT_CMD_CBLLEN32_G(x)	\

	(((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)



#define FW_PORT_CMD_AUXLINFO32_S	24

#define FW_PORT_CMD_AUXLINFO32_M	0xff

#define FW_PORT_CMD_AUXLINFO32_V(x)	((x) << FW_PORT_CMD_AUXLINFO32_S)

#define FW_PORT_CMD_AUXLINFO32_G(x)	\

	(((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)



#define FW_PORT_AUXLINFO32_KX4_S	2

#define FW_PORT_AUXLINFO32_KX4_M	0x1

#define FW_PORT_AUXLINFO32_KX4_V(x) \

	((x) << FW_PORT_AUXLINFO32_KX4_S)

#define FW_PORT_AUXLINFO32_KX4_G(x) \

	(((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)

#define FW_PORT_AUXLINFO32_KX4_F	FW_PORT_AUXLINFO32_KX4_V(1U)



#define FW_PORT_AUXLINFO32_KR_S	1

#define FW_PORT_AUXLINFO32_KR_M	0x1

#define FW_PORT_AUXLINFO32_KR_V(x) \

	((x) << FW_PORT_AUXLINFO32_KR_S)

#define FW_PORT_AUXLINFO32_KR_G(x) \

	(((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)

#define FW_PORT_AUXLINFO32_KR_F	FW_PORT_AUXLINFO32_KR_V(1U)



#define FW_PORT_CMD_MTU32_S	0

#define FW_PORT_CMD_MTU32_M	0xffff

#define FW_PORT_CMD_MTU32_V(x)	((x) << FW_PORT_CMD_MTU32_S)

#define FW_PORT_CMD_MTU32_G(x)	\

	(((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)



enum fw_port_type {

	FW_PORT_TYPE_FIBER_XFI,

	FW_PORT_TYPE_FIBER_XAUI,