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Commit c2cea8f6 authored by Ingrid Gallardo's avatar Ingrid Gallardo
Browse files

drm/msm/sde: add support to access hw irqs regs depending on revision 



Current code assumes that all the irqs registers
offsets can be access in all the hw revisions;
this is not the case for some targets that should
not access some of the irq registers.
This change adds the support to selectively remove
the irqs that are not supported in some of the
hw revisions.

Change-Id: Ic9d54864b515520bda39fad86c7b6cd29ff35db1
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent e1905eb4

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+4 −1
Original line number Diff line number Diff line
@@ -3559,13 +3559,16 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg, 


static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)

{

	int rc = 0;

	int i, rc = 0;



	if (!sde_cfg)

		return -EINVAL;



	rc = sde_hardware_format_caps(sde_cfg, hw_rev);



	for (i = 0; i < MDSS_INTR_MAX; i++)

		set_bit(i, sde_cfg->mdss_irqs);



	if (IS_MSM8996_TARGET(hw_rev)) {

		sde_cfg->perf.min_prefill_lines = 21;

	} else if (IS_MSM8998_TARGET(hw_rev)) {

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+24 −0
Original line number Diff line number Diff line
@@ -100,6 +100,27 @@ enum { 
#define IS_UBWC_30_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_30)



/**

 * SDE INTERRUPTS - maintains the possible hw irq's allowed by HW

 * The order in this enum must match the order of the irqs defined

 * by 'sde_irq_map'

 */

enum sde_intr_enum {

	MDSS_INTR_SSPP_TOP0_INTR,

	MDSS_INTR_SSPP_TOP0_INTR2,

	MDSS_INTR_SSPP_TOP0_HIST_INTR,

	MDSS_INTR_INTF_0_INTR,

	MDSS_INTR_INTF_1_INTR,

	MDSS_INTR_INTF_2_INTR,

	MDSS_INTR_INTF_3_INTR,

	MDSS_INTR_INTF_4_INTR,

	MDSS_INTR_AD4_0_INTR,

	MDSS_INTR_AD4_1_INTR,

	MDSS_INTF_TEAR_1_INTR,

	MDSS_INTF_TEAR_2_INTR,

	MDSS_INTR_MAX

};



/**

 * MDP TOP BLOCK features

 * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
@@ -1062,6 +1083,7 @@ struct sde_perf_cfg { 
 * @sui_ns_allowed      flag to indicate non-secure context banks are allowed

 *                         during secure-ui session

 * @sui_supported_blendstage  secure-ui supported blendstage

 * @mdss_irqs	  bitmap with the irqs supported by the target

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1169,6 +1191,8 @@ struct sde_mdss_cfg { 
	struct sde_format_extended *vig_formats;

	struct sde_format_extended *wb_formats;

	struct sde_format_extended *virt_vig_formats;



	DECLARE_BITMAP(mdss_irqs, MDSS_INTR_MAX);

};



struct sde_mdss_hw_cfg_handler {

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+682 −499

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/sde/sde_hw_interrupts.h

+5 −0
Original line number Diff line number Diff line
@@ -288,6 +288,9 @@ struct sde_hw_intr_ops { 
 * @save_irq_status:  array of IRQ status reg storage created during init

 * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts

 * @irq_lock:         spinlock for accessing IRQ resources

 * @sde_irq_size:   total number of elements of the sde_irq_tbl

 * @sde_irq_tbl:	table with the registesrs offsets of the sde interrupts

 *		supported by the hw

 */

struct sde_hw_intr {

	struct sde_hw_blk_reg_map hw;
@@ -295,6 +298,8 @@ struct sde_hw_intr { 
	u32 *cache_irq_mask;

	u32 *save_irq_status;

	u32 irq_idx_tbl_size;

	u32 sde_irq_size;

	struct sde_intr_reg *sde_irq_tbl;

	spinlock_t irq_lock;

};