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Commit c290dadf authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms/r7xx: add regs for 40 bit CUR/GRPH addresses 



The *_HIGH regs are reversed. The secondary ones are in the
primary block and vice versa.

We currently only use a 32 bit internal address, so these are
0 for now.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 33fdb15c

drivers/gpu/drm/radeon/atombios_crtc.c

+10 −0
Original line number Diff line number Diff line
@@ -577,6 +577,16 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 
		WREG32(AVIVO_D1VGA_CONTROL, 0);

	else

		WREG32(AVIVO_D2VGA_CONTROL, 0);



	if (rdev->family >= CHIP_RV770) {

		if (radeon_crtc->crtc_id) {

			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);

			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);

		} else {

			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);

			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);

		}

	}

	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

	       (u32) fb_location);

	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +

drivers/gpu/drm/radeon/r500_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -384,9 +384,16 @@ 
#       define AVIVO_D1GRPH_TILED                               (1 << 20)

#       define AVIVO_D1GRPH_MACRO_ADDRESS_MODE                  (1 << 21)



/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2

 * block and vice versa.  This applies to GRPH, CUR, etc.

 */

#define AVIVO_D1GRPH_LUT_SEL                                    0x6108

#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110

#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6914

#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6114

#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS                  0x6118

#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x691c

#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x611c

#define AVIVO_D1GRPH_PITCH                                      0x6120

#define AVIVO_D1GRPH_SURFACE_OFFSET_X                           0x6124

#define AVIVO_D1GRPH_SURFACE_OFFSET_Y                           0x6128
@@ -404,6 +411,8 @@ 
#       define AVIVO_D1CURSOR_MODE_MASK         (3 << 8)

#       define AVIVO_D1CURSOR_MODE_24BPP        2

#define AVIVO_D1CUR_SURFACE_ADDRESS             0x6408

#define R700_D1CUR_SURFACE_ADDRESS_HIGH         0x6c0c

#define R700_D2CUR_SURFACE_ADDRESS_HIGH         0x640c

#define AVIVO_D1CUR_SIZE                        0x6410

#define AVIVO_D1CUR_POSITION                    0x6414

#define AVIVO_D1CUR_HOT_SPOT                    0x6418

drivers/gpu/drm/radeon/radeon_cursor.c

+8 −2
Original line number Diff line number Diff line
@@ -109,9 +109,15 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	struct radeon_device *rdev = crtc->dev->dev_private;



	if (ASIC_IS_AVIVO(rdev))

	if (ASIC_IS_AVIVO(rdev)) {

		if (rdev->family >= CHIP_RV770) {

			if (radeon_crtc->crtc_id)

				WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0);

			else

				WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);

		}

		WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);

	else {

	} else {

		radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;

		/* offset is from DISP(2)_BASE_ADDRESS */

		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);