Commit c26f40da authored Dec 22, 2015 by Raanan Avargil Committed by Jeff Kirsher Feb 24, 2016

e1000e: Set HW FIFO minimum pointer gap for non-gig speeds



Based on feedback from HW team, the configured value of the internal PHY
HW FIFO pointer gap was incorrect for non-gig speeds.
This patch provides the correct configuration.

Signed-off-by: Raanan Avargil <raanan.avargil@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

parent 74f31299

drivers/net/ethernet/intel/e1000e/ich8lan.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -1479,6 +1479,18 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
		hw->phy.ops.release(hw);
		if (ret_val)
		return ret_val;
		} else {
		ret_val = hw->phy.ops.acquire(hw);
		if (ret_val)
		return ret_val;

		ret_val = e1e_wphy_locked(hw,
		PHY_REG(776, 20),
		0xC023);
		hw->phy.ops.release(hw);
		if (ret_val)
		return ret_val;

		}
		}
		}