Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c1f99c21 authored Dec 08, 2008 by Eric Miao

[ARM] pxafb: allow better platform configurable smart panel timing



For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:

  LCCR3_PCP - controls the L_PCLK_WR polarity
  LCCR3_HSP - controls the L_LCLK_A0 polarity
  LCCR3_VSP - controls the L_FCLK_RD polarity

To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:

  LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
  sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}

Signed-off-by: Eric Miao <eric.miao@marvell.com>

parent 07df1c4f

arch/arm/mach-pxa/include/mach/pxafb.h

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -95,6 +95,10 @@ struct pxafb_mode_info {
	* in pxa27x and pxa3xx, initialize them to the same value or		* in pxa27x and pxa3xx, initialize them to the same value or
	* the larger one will be used		* the larger one will be used
	* 3. same to {rd,wr}_pulse_width		* 3. same to {rd,wr}_pulse_width
			*
			* 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
			* 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
			* 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
	*/		*/
	unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */		unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
	unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */		unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */

drivers/video/pxafb.c

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -760,7 +760,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
	LCCR1_HorSnchWdth(__smart_timing(t3, lclk));		LCCR1_HorSnchWdth(__smart_timing(t3, lclk));

	fbi->reg_lccr2 = LCCR2_DisHght(var->yres);		fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
	fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));		fbi->reg_lccr3 = fbi->lccr3 \| LCCR3_PixClkDiv(__smart_timing(t4, lclk));
			fbi->reg_lccr3 \|= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
			fbi->reg_lccr3 \|= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;

	/* FIXME: make this configurable */		/* FIXME: make this configurable */
	fbi->reg_cmdcr = 1;		fbi->reg_cmdcr = 1;