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Commit c1bfa985 authored by Murali Karicheri's avatar Murali Karicheri Committed by Olof Johansson
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ARM: dts: keystone: fix dt bindings to use post div register for mainpll 



All of the keystone devices have a separate register to hold post
divider value for main pll clock. Currently the fixed-postdiv
value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
use a value of 2 for this. Now that we have fixed this in the pll
clock driver change the dt bindings for the same.

Signed-off-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Acked-by: default avatarSantosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent a7dae155

arch/arm/boot/dts/k2e-clocks.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -13,9 +13,8 @@ clocks { 
		#clock-cells = <0>;

		compatible = "ti,keystone,main-pll-clock";

		clocks = <&refclksys>;

		reg = <0x02620350 4>, <0x02310110 4>;

		reg-names = "control", "multiplier";

		fixed-postdiv = <2>;

		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;

		reg-names = "control", "multiplier", "post-divider";

	};



	papllclk: papllclk@2620358 {

arch/arm/boot/dts/k2hk-clocks.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -22,9 +22,8 @@ clocks { 
		#clock-cells = <0>;

		compatible = "ti,keystone,main-pll-clock";

		clocks = <&refclksys>;

		reg = <0x02620350 4>, <0x02310110 4>;

		reg-names = "control", "multiplier";

		fixed-postdiv = <2>;

		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;

		reg-names = "control", "multiplier", "post-divider";

	};



	papllclk: papllclk@2620358 {

arch/arm/boot/dts/k2l-clocks.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -22,9 +22,8 @@ clocks { 
		#clock-cells = <0>;

		compatible = "ti,keystone,main-pll-clock";

		clocks = <&refclksys>;

		reg = <0x02620350 4>, <0x02310110 4>;

		reg-names = "control", "multiplier";

		fixed-postdiv = <2>;

		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;

		reg-names = "control", "multiplier", "post-divider";

	};



	papllclk: papllclk@2620358 {