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Commit c1b68c71 authored by Marc Zyngier's avatar Marc Zyngier Committed by Greg Kroah-Hartman
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KVM: arm64: Introduce handling of AArch32 TTBCR2 traps 



commit ca4e514774930f30b66375a974b5edcbebaf0e7e upstream.

ARMv8.2 introduced TTBCR2, which shares TCR_EL1 with TTBCR.
Gracefully handle traps to this register when HCR_EL2.TVM is set.

Cc: stable@vger.kernel.org
Reported-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 338b6021

arch/arm64/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -165,6 +165,7 @@ enum vcpu_sysreg { 
#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */

#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */

#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */

#define c2_TTBCR2	(c2_TTBCR + 1)	/* Translation Table Base Control R. 2 */

#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */

#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */

#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */

arch/arm64/kvm/sys_regs.c

+1 −0
Original line number Diff line number Diff line
@@ -1661,6 +1661,7 @@ static const struct sys_reg_desc cp15_regs[] = { 
	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },

	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },

	{ Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },

	{ Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },

	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },

	{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },

	{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },