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Commit c1b30e4d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control changes from Linus Walleij:
 "Here is a stash of pin control changes I have collected for the v3.19
  series.  Mainly new hardware support, with Intels new embedded SoC as
  the especially interesting thing standing out, fully using the
  subsystem.

   - Force conversion of the ux500 pin control device trees and parsers
     to use the generic pin control bindings.
   - New driver and device tree bindings for the Qualcomm PMIC MPP pin
     controller and GPIO.
   - Some ACPI infrastructure for pin controllers.
   - New driver for the Intel CherryView/Braswell pin controller, the
     first Intel pin controller to fully take advantage of the pin
     control subsystem.
   - Support the Freescale i.MX VF610 variant.
   - Support the sunxi A80 variant.
   - Support the Samsung Exynos 4415 and Exynos 7 variants.
   - Split out Intel pin controllers to their own subdirectory.
   - A large slew of rockchip pin control updates, including
     suspend/resume support.
   - A large slew of Samsung Exynos pin controller updates.
   - Various minor updates and fixes"

* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
  pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
  pinctrl: meson: add device tree bindings documentation
  gpio: tz1090: Fix error handling of irq_of_parse_and_map
  pinctrl: tz1090-pinctrl.txt: Fix typo in binding
  pinctrl: pinconf-generic: Declare dt_params/conf_items const
  pinctrl: exynos: Add support for Exynos4415
  pinctrl: exynos: Add initial driver data for Exynos7
  pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
  pinctrl: exynos: Consolidate irq domain callbacks
  pinctrl: exynos: Generalize the eint16_31 demux code
  pinctrl: samsung: Separate per-bank init and runtime data
  pinctrl: samsung: Constify samsung_pin_ctrl struct
  pinctrl: samsung: Constify samsung_pin_bank_type struct
  pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
  pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
  pinctrl: Add Intel Cherryview/Braswell pin controller support
  gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
  pinctrl: Fix path error in documentation
  pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
  pinctrl: rockchip: add suspend/resume functions
  ...
parents 92a578b0 853b6bf0

Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt

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@@ -67,7 +67,7 @@ Valid values for pin and group names are: 
    They also all support the some form of muxing. Any pins which are contained

    in one of the mux groups (see below) can be muxed only to the functions

    supported by the mux group. All other pins can be muxed to the "perip"

    function which which enables them with their intended peripheral.

    function which enables them with their intended peripheral.



    Different pins in the same mux group cannot be muxed to different functions,

    however it is possible to mux only a subset of the pins in a mux group to a

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt

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== Amlogic Meson pinmux controller ==



Required properties for the root node:

 - compatible: "amlogic,meson8-pinctrl"

 - reg: address and size of registers controlling irq functionality



=== GPIO sub-nodes ===



The 2 power domains of the controller (regular and always-on) are

represented as sub-nodes and each of them acts as a GPIO controller.



Required properties for sub-nodes are:

 - reg: should contain address and size for mux, pull-enable, pull and

   gpio register sets

 - reg-names: an array of strings describing the "reg" entries. Must

   contain "mux", "pull" and "gpio". "pull-enable" is optional and

   when it is missing the "pull" registers are used instead

 - gpio-controller: identifies the node as a gpio controller

 - #gpio-cells: must be 2



Valid sub-node names are:

 - "banks" for the regular domain

 - "ao-bank" for the always-on domain



=== Other sub-nodes ===



Child nodes without the "gpio-controller" represent some desired

configuration for a pin or a group. Those nodes can be pinmux nodes or

configuration nodes.



Required properties for pinmux nodes are:

 - groups: a list of pinmux groups. The list of all available groups

   depends on the SoC and can be found in driver sources.

 - function: the name of a function to activate for the specified set

   of groups. The list of all available functions depends on the SoC

   and can be found in driver sources.



Required properties for configuration nodes:

 - pins: a list of pin names



Configuration nodes support the generic properties "bias-disable",

"bias-pull-up" and "bias-pull-down", described in file

pinctrl-bindings.txt



=== Example ===



	pinctrl: pinctrl@c1109880 {

		compatible = "amlogic,meson8-pinctrl";

		reg = <0xc1109880 0x10>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		gpio: banks@c11080b0 {

			reg = <0xc11080b0 0x28>,

			      <0xc11080e8 0x18>,

			      <0xc1108120 0x18>,

			      <0xc1108030 0x30>;

			reg-names = "mux", "pull", "pull-enable", "gpio";

			gpio-controller;

			#gpio-cells = <2>;

               };



		gpio_ao: ao-bank@c1108030 {

			reg = <0xc8100014 0x4>,

			      <0xc810002c 0x4>,

			      <0xc8100024 0x8>;

			reg-names = "mux", "pull", "gpio";

			gpio-controller;

			#gpio-cells = <2>;

		};



		nand {

			mux {

				groups = "nand_io", "nand_io_ce0", "nand_io_ce1",

					 "nand_io_rb0", "nand_ale", "nand_cle",

					 "nand_wen_clk", "nand_ren_clk", "nand_dqs",

					 "nand_ce2", "nand_ce3";

				function = "nand";

			};

		};



		uart_ao_a {

			mux {

				groups = "uart_tx_ao_a", "uart_rx_ao_a",

					 "uart_cts_ao_a", "uart_rts_ao_a";

				function = "uart_ao";

			};



			conf {

				pins = "GPIOAO_0", "GPIOAO_1",

				       "GPIOAO_2", "GPIOAO_3";

				bias-disable;

			};

		};

	};

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

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@@ -216,4 +216,4 @@ arguments are described below. 
  or 0 to disable debouncing



More in-depth documentation on these parameters can be found in

<include/linux/pinctrl/pinconfig-generic.h>
 
<include/linux/pinctrl/pinconf-generic.h>

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt

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Qualcomm PMIC GPIO block



This binding describes the GPIO block(s) found in the 8xxx series of

PMIC's from Qualcomm.



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		    "qcom,pm8018-gpio"

		    "qcom,pm8038-gpio"

		    "qcom,pm8058-gpio"

		    "qcom,pm8917-gpio"

		    "qcom,pm8921-gpio"

		    "qcom,pm8941-gpio"

		    "qcom,pma8084-gpio"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Register base of the GPIO block and length.



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Must contain an array of encoded interrupt specifiers for

		    each available GPIO



- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: Mark the device node as a GPIO controller



- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: Must be 2;

		    the first cell will be used to define gpio number and the

		    second denotes the flags for this gpio



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin or a list of pins. This configuration can include the

mux function to select on those pin(s), and various pin configuration

parameters, as listed below.





SUBNODES:



The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.



The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:



- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of gpio pins affected by the properties specified in

		    this subnode.  Valid pins are:

		    gpio1-gpio6 for pm8018

		    gpio1-gpio12 for pm8038

		    gpio1-gpio40 for pm8058

		    gpio1-gpio38 for pm8917

		    gpio1-gpio44 for pm8921

		    gpio1-gpio36 for pm8941

		    gpio1-gpio22 for pma8084



- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins.  Valid values are:

		    "normal",

		    "paired",

		    "func1",

		    "func2",

		    "dtest1",

		    "dtest2",

		    "dtest3",

		    "dtest4"



- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as no pull.



- bias-pull-down:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull down.



- bias-pull-up:

	Usage: optional

	Value type: <empty>

	Definition: The specified pins should be configured as pull up.



- qcom,pull-up-strength:

	Usage: optional

	Value type: <u32>

	Definition: Specifies the strength to use for pull up, if selected.

		    Valid values are; as defined in

		    <dt-bindings/pinctrl/qcom,pmic-gpio.h>:

		    1: 30uA                     (PMIC_GPIO_PULL_UP_30)

		    2: 1.5uA                    (PMIC_GPIO_PULL_UP_1P5)

		    3: 31.5uA                   (PMIC_GPIO_PULL_UP_31P5)

		    4: 1.5uA + 30uA boost       (PMIC_GPIO_PULL_UP_1P5_30)

		    If this property is ommited 30uA strength will be used if

		    pull up is selected



- bias-high-impedance:

	Usage: optional

	Value type: <none>

	Definition: The specified pins will put in high-Z mode and disabled.



- input-enable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are put in input mode.



- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.



- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.



- power-source:

	Usage: optional

	Value type: <u32>

	Definition: Selects the power source for the specified pins. Valid

		    power sources are defined per chip in

		    <dt-bindings/pinctrl/qcom,pmic-gpio.h>



- qcom,drive-strength:

	Usage: optional

	Value type: <u32>

	Definition: Selects the drive strength for the specified pins. Value

		    drive strengths are:

		    0: no (PMIC_GPIO_STRENGTH_NO)

		    1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V

		    2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V

		    3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V

		    as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>



- drive-push-pull:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in push-pull mode.



- drive-open-drain:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in open-drain mode.



- drive-open-source:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in open-source mode.



Example:



	pm8921_gpio: gpio@150 {

		compatible = "qcom,pm8921-gpio";

		reg = <0x150 0x160>;

		interrupts = <192 1>, <193 1>, <194 1>,

			     <195 1>, <196 1>, <197 1>,

			     <198 1>, <199 1>, <200 1>,

			     <201 1>, <202 1>, <203 1>,

			     <204 1>, <205 1>, <206 1>,

			     <207 1>, <208 1>, <209 1>,

			     <210 1>, <211 1>, <212 1>,

			     <213 1>, <214 1>, <215 1>,

			     <216 1>, <217 1>, <218 1>,

			     <219 1>, <220 1>, <221 1>,

			     <222 1>, <223 1>, <224 1>,

			     <225 1>, <226 1>, <227 1>,

			     <228 1>, <229 1>, <230 1>,

			     <231 1>, <232 1>, <233 1>,

			     <234 1>, <235 1>;



		gpio-controller;

		#gpio-cells = <2>;



		pm8921_gpio_keys: gpio-keys {

			volume-keys {

				pins = "gpio20", "gpio21";

				function = "normal";



				input-enable;

				bias-pull-up;

				drive-push-pull;

				qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;

				power-source = <PM8921_GPIO_S4>;

			};

		};

	};

Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt

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Qualcomm PMIC Multi-Purpose Pin (MPP) block



This binding describes the MPP block(s) found in the 8xxx series

of PMIC's from Qualcomm.



- compatible:

	Usage: required

	Value type: <string>

	Definition: Should contain one of:

		    "qcom,pm8841-mpp",

		    "qcom,pm8941-mpp",

		    "qcom,pma8084-mpp",



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Register base of the MPP block and length.



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Must contain an array of encoded interrupt specifiers for

		    each available MPP



- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: Mark the device node as a GPIO controller



- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: Must be 2;

		    the first cell will be used to define MPP number and the

		    second denotes the flags for this MPP



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin or a list of pins. This configuration can include the

mux function to select on those pin(s), and various pin configuration

parameters, as listed below.



SUBNODES:



The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.



The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:



- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of MPP pins affected by the properties specified in

		    this subnode.  Valid pins are:

		    mpp1-mpp4 for pm8841

		    mpp1-mpp8 for pm8941

		    mpp1-mpp4 for pma8084



- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins.  Valid values are:

		    "normal",

		    "paired",

		    "dtest1",

		    "dtest2",

		    "dtest3",

		    "dtest4"



- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as no pull.



- bias-pull-up:

	Usage: optional

	Value type: <u32>

	Definition: The specified pins should be configured as pull up.

		    Valid values are 600, 10000 and 30000 in bidirectional mode

		    only, i.e. when operating in qcom,analog-mode and input and

		    outputs are enabled. The hardware ignores the configuration

		    when operating in other modes.



- bias-high-impedance:

	Usage: optional

	Value type: <none>

	Definition: The specified pins will put in high-Z mode and disabled.



- input-enable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are put in input mode, i.e. their input

		    buffer is enabled



- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.



- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.



- power-source:

	Usage: optional

	Value type: <u32>

	Definition: Selects the power source for the specified pins. Valid power

		    sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>



- qcom,analog-mode:

	Usage: optional

	Value type: <none>

	Definition: Selects Analog mode of operation: combined with input-enable

		    and/or output-high, output-low MPP could operate as

		    Bidirectional Logic, Analog Input, Analog Output.



- qcom,amux-route:

	Usage: optional

	Value type: <u32>

	Definition: Selects the source for analog input. Valid values are

		    defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>

		    PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...



Example:



	mpps@a000 {

		compatible = "qcom,pm8841-mpp";

		reg = <0xa000>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>;



		pinctrl-names = "default";

		pinctrl-0 = <&pm8841_default>;



		pm8841_default: default {

			gpio {

				pins = "mpp1", "mpp2", "mpp3", "mpp4";

				function = "normal";

				input-enable;

				power-source = <PM8841_MPP_S3>;

			};

		};

	};