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Commit c18b78ed authored by Manish Dusane's avatar Manish Dusane Committed by James Bottomley
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[SCSI] qla4xxx: Take E-port out of reset before disabling pause frames



Problem Description:
Disabling pause frames might cause hardware wedging needing a power cycle.
This might happen if the Eport is not initialized and is in reset.

Solution:
Before disabling pause frames ensure that eport is out of reset.

Signed-off-by: default avatarManish Dusane <manish.dusane@qlogic.com>
Signed-off-by: default avatarVikas Chaudhary <vikas.chaudhary@qlogic.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 27db682b
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+28 −0
Original line number Diff line number Diff line
@@ -1629,9 +1629,37 @@ static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha)
	ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n");
}

/**
 * qla4_83xx_eport_init - Initialize EPort.
 * @ha: Pointer to host adapter structure.
 *
 * If EPort hardware is in reset state before disabling pause, there would be
 * serious hardware wedging issues. To prevent this perform eport init everytime
 * before disabling pause frames.
 **/
static void qla4_83xx_eport_init(struct scsi_qla_host *ha)
{
	/* Clear the 8 registers */
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0);
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0);

	/* Write any value to Reset Control register */
	qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF);

	ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n");
}

void qla4_83xx_disable_pause(struct scsi_qla_host *ha)
{
	ha->isp_ops->idc_lock(ha);
	/* Before disabling pause frames, ensure that eport is not in reset */
	qla4_83xx_eport_init(ha);
	qla4_83xx_dump_pause_control_regs(ha);
	__qla4_83xx_disable_pause(ha);
	ha->isp_ops->idc_unlock(ha);
+10 −0
Original line number Diff line number Diff line
@@ -55,6 +55,16 @@
#define QLA83XX_SET_PAUSE_VAL		0x0
#define QLA83XX_SET_TC_MAX_CELL_VAL	0x03FF03FF

#define QLA83XX_RESET_CONTROL		0x28084E50
#define QLA83XX_RESET_REG		0x28084E60
#define QLA83XX_RESET_PORT0		0x28084E70
#define QLA83XX_RESET_PORT1		0x28084E80
#define QLA83XX_RESET_PORT2		0x28084E90
#define QLA83XX_RESET_PORT3		0x28084EA0
#define QLA83XX_RESET_SRE_SHIM		0x28084EB0
#define QLA83XX_RESET_EPG_SHIM		0x28084EC0
#define QLA83XX_RESET_ETHER_PCS		0x28084ED0

/* qla_83xx_reg_tbl registers */
#define QLA83XX_PEG_HALT_STATUS1	0x34A8
#define QLA83XX_PEG_HALT_STATUS2	0x34AC