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Commit c16e78b8 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Andy Gross
Browse files

arm64: dts: msm8916: fix gic_irq_domain_translate warnings 



Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarThierry Escande <thierry.escande@linaro.org>
Tested-by: default avatarThierry Escande <thierry.escande@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 290fa8d7

arch/arm64/boot/dts/qcom/msm8916.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ 


	pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;

	};



	thermal-zones {
@@ -512,7 +512,7 @@ 
		blsp_i2c2: i2c@78b6000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b6000 0x500>;

			interrupts = <GIC_SPI 96 0>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";
@@ -527,7 +527,7 @@ 
		blsp_i2c4: i2c@78b8000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b8000 0x500>;

			interrupts = <GIC_SPI 98 0>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;

			clock-names = "iface", "core";
@@ -542,7 +542,7 @@ 
		blsp_i2c6: i2c@78ba000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078ba000 0x500>;

			interrupts = <GIC_SPI 100 0>;

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;

			clock-names = "iface", "core";
@@ -574,7 +574,7 @@ 
					"mi2s-bit-clk3";

			#sound-dai-cells = <1>;



			interrupts = <0 160 0>;

			interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "lpass-irq-lpaif";

			reg = <0x07708000 0x10000>;

			reg-names = "lpass-lpaif";
@@ -594,7 +594,7 @@ 
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;

			reg-names = "hc_mem", "core_mem";



			interrupts = <0 123 0>, <0 138 0>;

			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,
@@ -611,7 +611,7 @@ 
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;

			reg-names = "hc_mem", "core_mem";



			interrupts = <0 125 0>, <0 221 0>;

			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,
@@ -818,7 +818,7 @@ 
			iommu-ctx@2000 {

				compatible = "qcom,msm-iommu-v1-ns";

				reg = <0x2000 0x1000>;

				interrupts = <GIC_SPI 242 0>;

				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -862,7 +862,7 @@ 
				      "bus_clk",

				      "vsync_clk";



			interrupts = <0 72 0>;

			interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;



			interrupt-controller;

			#interrupt-cells = <1>;