ath9k: Try to fix whitespace damage (c16c9d06) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/net/wireless/ath/ath9k/eeprom.c

+121 −130

Original line number	Diff line number	Diff line
		@@ -2854,7 +2854,6 @@ static struct eeprom_ops eep_def_ops = {
		.get_spur_channel = ath9k_hw_def_get_spur_channel
		};


		static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
		{
		return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
		@@ -2871,6 +2870,7 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
		u16 *eep_data;
		int addr, eep_start_loc = AR9287_EEP_START_LOC;
		eep_data = (u16 *)eep;

		if (!ath9k_hw_use_flash(ah)) {
		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
		"Reading from EEPROM, not flash\n");
		@@ -2887,6 +2887,7 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
		}
		return true;
		}

		static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
		{
		u32 sum = 0, el, integer;
		@@ -3059,6 +3060,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
		{
		#define TMP_VAL_VPD_TABLE \
		((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));

		int i, j, k;
		int16_t ss;
		u16 idxL = 0, idxR = 0, numPiers;
		@@ -3079,6 +3081,7 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];

		ath9k_hw_get_channel_centers(ah, chan, &centers);

		for (numPiers = 0; numPiers < availPiers; numPiers++) {
		if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
		break;
		@@ -3214,7 +3217,9 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
		u16 idxL = 0, idxR = 0, numPiers;
		bool match;
		struct chan_centers centers;

		ath9k_hw_get_channel_centers(ah, chan, &centers);

		for (numPiers = 0; numPiers < availPiers; numPiers++) {
		if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
		break;
		@@ -3272,9 +3277,9 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
		}
		}


		static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
		struct ath9k_channel chan, int16_t pTxPowerIndexOffset)
		struct ath9k_channel *chan,
		int16_t *pTxPowerIndexOffset)
		{
		struct cal_data_per_freq_ar9287 *pRawDataset;
		struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
		@@ -3430,7 +3435,6 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
		*pTxPowerIndexOffset = 0;
		}


		static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		struct ath9k_channel chan, int16_t ratesArray, u16 cfgCtl,
		u16 AntennaReduction, u16 twiceMaxRegulatoryPower,
		@@ -3440,8 +3444,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10

		u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
		static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9,
		AR5416_MAX_RATE_POWER };
		static const u16 tpScaleReductionTable[5] =
		{ 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
		int i;
		int16_t twiceLargestAntenna;
		struct cal_ctl_data_ar9287 *rep;
		@@ -3452,8 +3456,9 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		struct cal_target_power_ht targetPowerHt20,
		targetPowerHt40 = {0, {0, 0, 0, 0} };
		u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
		u16 ctlModesFor11g[] = {CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
		CTL_11G_EXT, CTL_2GHT40};
		u16 ctlModesFor11g[] =
		{CTL_11B, CTL_11G, CTL_2GHT20,
		CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
		u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
		struct chan_centers centers;
		int tx_chainmask;
		@@ -3489,8 +3494,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		scaledPower = max((u16)0, scaledPower);

		if (IS_CHAN_2GHZ(chan)) {
		numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
		SUB_NUM_CTL_MODES_AT_2G_40;
		numCtlModes =
		ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
		pCtlMode = ctlModesFor11g;

		ath9k_hw_get_legacy_target_powers(ah, chan,
		@@ -3524,7 +3529,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		}

		for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {

		bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) \|\|
		(pCtlMode[ctlMode] == CTL_2GHT40);
		if (isHt40CtlMode)
		@@ -3534,14 +3538,15 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		else
		freq = centers.ctl_center;


		if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
		ah->eep_ops->get_eeprom_rev(ah) <= 2)
		twiceMaxEdgePower = AR5416_MAX_RATE_POWER;

		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
		"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d,"
		"EXT_ADDITIVE %d\n", ctlMode, numCtlModes,
		isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE));

		for (i = 0; (i < AR9287_NUM_CTLS)
		&& pEepData->ctlIndex[i]; i++) {
		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
		@@ -3592,7 +3597,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
		scaledPower, minCtlPower);


		switch (pCtlMode[ctlMode]) {

		case CTL_11B:
		@@ -3650,9 +3654,13 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		}
		}

		ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
		ratesArray[rate18mb] = ratesArray[rate24mb] =
		ratesArray[rate6mb] =
		ratesArray[rate9mb] =
		ratesArray[rate12mb] =
		ratesArray[rate18mb] =
		ratesArray[rate24mb] =
		targetPowerOfdm.tPow2x[0];

		ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
		ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
		ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
		@@ -3680,23 +3688,27 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
		if (IS_CHAN_2GHZ(chan))
		ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
		}

		#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
		#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
		}

		static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		struct ath9k_channel *chan, u16 cfgCtl,
		u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower,
		u8 twiceAntennaReduction,
		u8 twiceMaxRegulatoryPower,
		u8 powerLimit)
		{
		#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
		#define INCREASE_MAXPOW_BY_THREE_CHAIN 10

		struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
		struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
		int16_t ratesArray[Ar5416RateSize];
		int16_t txPowerIndexOffset = 0;
		u8 ht40PowerIncForPdadc = 2;
		int i;

		memset(ratesArray, 0, sizeof(ratesArray));

		if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
		@@ -3709,7 +3721,6 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		twiceMaxRegulatoryPower,
		powerLimit);


		ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset);

		for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
		@@ -3723,49 +3734,42 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
		}


		REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
		ATH9K_POW_SM(ratesArray[rate18mb], 24)
		\| ATH9K_POW_SM(ratesArray[rate12mb], 16)
		\| ATH9K_POW_SM(ratesArray[rate9mb], 8)
		\| ATH9K_POW_SM(ratesArray[rate6mb], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rate6mb], 0));

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
		ATH9K_POW_SM(ratesArray[rate54mb], 24)
		\| ATH9K_POW_SM(ratesArray[rate48mb], 16)
		\| ATH9K_POW_SM(ratesArray[rate36mb], 8)
		\| ATH9K_POW_SM(ratesArray[rate24mb], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rate24mb], 0));

		if (IS_CHAN_2GHZ(chan)) {
		REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
		ATH9K_POW_SM(ratesArray[rate2s], 24)
		\| ATH9K_POW_SM(ratesArray[rate2l], 16)
		\| ATH9K_POW_SM(ratesArray[rateXr], 8)
		\| ATH9K_POW_SM(ratesArray[rate1l], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rate1l], 0));
		REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
		ATH9K_POW_SM(ratesArray[rate11s], 24)
		\| ATH9K_POW_SM(ratesArray[rate11l], 16)
		\| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
		\| ATH9K_POW_SM(ratesArray[rate5_5l], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
		}

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
		ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
		\| ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
		\| ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
		\| ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rateHt20_0], 0));

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
		ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
		\| ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
		\| ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
		\| ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rateHt20_4], 0));

		if (IS_CHAN_HT40(chan)) {
		if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
		@@ -3773,15 +3777,13 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
		\| ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
		\| ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
		\| ATH9K_POW_SM(ratesArray[rateHt40_0], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rateHt40_0], 0));

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
		ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
		\| ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
		\| ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
		\| ATH9K_POW_SM(ratesArray[rateHt40_4], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
		} else {
		REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
		ATH9K_POW_SM(ratesArray[rateHt40_3] +
		@@ -3791,8 +3793,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		\| ATH9K_POW_SM(ratesArray[rateHt40_1] +
		ht40PowerIncForPdadc, 8)
		\| ATH9K_POW_SM(ratesArray[rateHt40_0] +
		ht40PowerIncForPdadc, 0)
		);
		ht40PowerIncForPdadc, 0));

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
		ATH9K_POW_SM(ratesArray[rateHt40_7] +
		@@ -3802,20 +3803,16 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		\| ATH9K_POW_SM(ratesArray[rateHt40_5] +
		ht40PowerIncForPdadc, 8)
		\| ATH9K_POW_SM(ratesArray[rateHt40_4] +
		ht40PowerIncForPdadc, 0)
		);

		ht40PowerIncForPdadc, 0));
		}

		REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
		ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
		\| ATH9K_POW_SM(ratesArray[rateExtCck], 16)
		\| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
		\| ATH9K_POW_SM(ratesArray[rateDupCck], 0)
		);
		\| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
		}


		if (IS_CHAN_2GHZ(chan))
		i = rate1l;
		else
		@@ -3848,7 +3845,6 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
		static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah,
		struct ath9k_channel *chan)
		{
		return;
		}

		static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
		@@ -3856,7 +3852,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
		{
		struct ar9287_eeprom *eep = &ah->eeprom.map9287;
		struct modal_eep_ar9287_header *pModal = &eep->modalHeader;

		u16 antWrites[AR9287_ANT_16S];
		u32 regChainOffset;
		u8 txRxAttenLocal;
		@@ -3886,7 +3881,6 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
		antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
		}


		REG_WRITE(ah, AR_PHY_SWITCH_COM,
		ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));

		@@ -4000,18 +3994,15 @@ static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah,
		return 1;
		}




		static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
		struct ath9k_channel *chan)
		{
		struct ar9287_eeprom *eep = &ah->eeprom.map9287;
		struct modal_eep_ar9287_header *pModal = &eep->modalHeader;

		return pModal->antCtrlCommon & 0xFFFF;
		}


		static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
		u16 i, bool is2GHz)
		{
		@@ -4055,10 +4046,10 @@ static struct eeprom_ops eep_AR9287_ops = {
		.get_spur_channel = ath9k_hw_AR9287_get_spur_channel
		};


		int ath9k_hw_eeprom_init(struct ath_hw *ah)
		{
		int status;

		if (AR_SREV_9287(ah)) {
		ah->eep_map = EEP_MAP_AR9287;
		ah->eep_ops = &eep_AR9287_ops;

drivers/net/wireless/ath/ath9k/eeprom.h

+94 −99

Original line number	Diff line number	Diff line
		@@ -421,7 +421,6 @@ struct modal_eep_4k_header {
		u16 db1_234;
		u16 db2_234;
		u8 futureModal[4];

		struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
		} __packed;

		@@ -483,8 +482,6 @@ struct modal_eep_ar9287_header {
		struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
		} __packed;



		struct cal_data_per_freq {
		u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
		u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
		@@ -525,7 +522,6 @@ struct cal_data_op_loop_ar9287 {
		u8 empty[2][5];
		} __packed;


		struct cal_data_per_freq_ar9287 {
		u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
		u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
		@@ -620,7 +616,6 @@ struct ar9287_eeprom {
		u8 padding;
		} __packed;


		enum reg_ext_bitmap {
		REG_EXT_JAPAN_MIDBAND = 1,
		REG_EXT_FCC_DFS_HT40 = 2,