Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c168ac27 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Miquel Raynal
Browse files

dt-bindings: qcom_nandc: update for ECC strength and step size 



1. If nand-ecc-strength specified in DT, then controller will use
   this ECC strength otherwise ECC strength will be calculated
   according to chip requirement and available OOB size.

2. QCOM NAND controller supports only one step size (512 bytes) but
   nand-ecc-step-size is required property in DT. This DT property
   can be removed and ecc step size can be assigned in driver with
   512 bytes value.

Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent f9801fda

Documentation/devicetree/bindings/mtd/qcom_nandc.txt

+3 −4
Original line number Diff line number Diff line
@@ -45,11 +45,12 @@ Required properties: 
			number (e.g., 0, 1, 2, etc.)

- #address-cells:	see partition.txt

- #size-cells:		see partition.txt

- nand-ecc-strength:	see nand.txt

- nand-ecc-step-size:	must be 512. see nand.txt for more details.



Optional properties:

- nand-bus-width:	see nand.txt

- nand-ecc-strength:	see nand.txt. If not specified, then ECC strength will

			be used according to chip requirement and available

			OOB size.



Each nandcs device node may optionally contain a 'partitions' sub-node, which

further contains sub-nodes describing the flash partition mapping. See
@@ -77,7 +78,6 @@ nand-controller@1ac00000 { 
		reg = <0>;



		nand-ecc-strength = <4>;

		nand-ecc-step-size = <512>;

		nand-bus-width = <8>;



		partitions {
@@ -117,7 +117,6 @@ nand-controller@79b0000 { 
	nand@0 {

		reg = <0>;

		nand-ecc-strength = <4>;

		nand-ecc-step-size = <512>;

		nand-bus-width = <8>;



		partitions {