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Commit c149dcb5 authored by Jani Nikula's avatar Jani Nikula Committed by Takashi Iwai
Browse files

drm/i915: provide interface for audio driver to query cdclk 



For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So provide a private interface for the
audio driver to query CDCLK.

This is a stopgap solution until a more generic interface between audio
and display drivers has been implemented.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarMengdong Lin <mengdong.lin@intel.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent a12137e7

drivers/gpu/drm/i915/intel_pm.c

+21 −0
Original line number Diff line number Diff line
@@ -6053,6 +6053,27 @@ int i915_release_power_well(void) 
}

EXPORT_SYMBOL_GPL(i915_release_power_well);



/*

 * Private interface for the audio driver to get CDCLK in kHz.

 *

 * Caller must request power well using i915_request_power_well() prior to

 * making the call.

 */

int i915_get_cdclk_freq(void)

{

	struct drm_i915_private *dev_priv;



	if (!hsw_pwr)

		return -ENODEV;



	dev_priv = container_of(hsw_pwr, struct drm_i915_private,

				power_domains);



	return intel_ddi_get_cdclk_freq(dev_priv);

}

EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);





#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)



#define HSW_ALWAYS_ON_POWER_DOMAINS (			\

include/drm/i915_powerwell.h

+1 −0
Original line number Diff line number Diff line
@@ -32,5 +32,6 @@ 
/* For use by hda_i915 driver */

extern int i915_request_power_well(void);

extern int i915_release_power_well(void);

extern int i915_get_cdclk_freq(void);



#endif				/* _I915_POWERWELL_H_ */