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Commit c1152a62 authored by Deepak Kumar's avatar Deepak Kumar
Browse files

msm: kgsl: Don't disable TSESkip logic for all A6XX GPUs 



TSESkip logic is not correctly functioning only on few
A6XX GPUs but in current code its disabled for all A6XX
cores. Add support to disable this feature only for those
cores where this feature is not working to allow other
cores to still take benefit of this feature.

Change-Id: I0f73a88760378c43978f1a7ee14272ebb303d3a2
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent cfdc3af3

drivers/gpu/msm/adreno-gpulist.h

+5 −0
Original line number Diff line number Diff line
@@ -1047,6 +1047,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
	.veto_fal10 = true,

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

};



static const struct adreno_reglist a640_hwcg_regs[] = {
@@ -1135,6 +1136,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

};



static const struct adreno_reglist a650_hwcg_regs[] = {
@@ -1214,6 +1216,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
	.pdc_in_aop = true,

	.hang_detect_cycles = 0x3fffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

};



static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
@@ -1241,6 +1244,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
	.pdc_in_aop = true,

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

};



static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
@@ -1266,6 +1270,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

};



static const struct adreno_reglist a612_hwcg_regs[] = {

drivers/gpu/msm/adreno_a6xx.c

+2 −1
Original line number Diff line number Diff line
@@ -540,6 +540,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
		kgsl_regrmw(device, A6XX_PC_DBG_ECO_CNTL, 0, (1 << 8));



	/* Set the bit vccCacheSkipDis=1 to get rid of TSEskip logic */

	if (a6xx_core->disable_tseskip)

		kgsl_regrmw(device, A6XX_PC_DBG_ECO_CNTL, 0, (1 << 9));



	/* Enable the GMEM save/restore feature for preemption */

drivers/gpu/msm/adreno_a6xx.h

+2 −0
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ struct adreno_a6xx_core { 
	u32 hang_detect_cycles;

	/** @protected_regs: Array of protected registers for the target */

	const struct a6xx_protected_regs *protected_regs;

	/** @disable_tseskip: True if TSESkip logic is disabled */

	bool disable_tseskip;

};



#define CP_CLUSTER_FE		0x0