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Commit c0d96aed authored by Jason Chen's avatar Jason Chen Committed by Sascha Hauer
Browse files

MXC PWM: should active during DOZE/WAIT/DBG mode 



Signed-off-by: default avatarJason Chen <jason.chen@linaro.org>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Cc: stable@kernel.org
parent 5611cc45

arch/arm/plat-mxc/pwm.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -32,6 +32,9 @@ 
#define MX3_PWMSAR                0x0C    /* PWM Sample Register */

#define MX3_PWMSAR                0x0C    /* PWM Sample Register */

#define MX3_PWMPR                 0x10    /* PWM Period Register */

#define MX3_PWMPR                 0x10    /* PWM Period Register */

#define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)

#define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)

#define MX3_PWMCR_DOZEEN                (1 << 24)

#define MX3_PWMCR_WAITEN                (1 << 23)

#define MX3_PWMCR_DBGEN			(1 << 22)

#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)

#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)

#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)

#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)

#define MX3_PWMCR_EN              (1 << 0)

#define MX3_PWMCR_EN              (1 << 0)
@@ -77,7 +80,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) 
		writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);

		writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);

		writel(period_cycles, pwm->mmio_base + MX3_PWMPR);

		writel(period_cycles, pwm->mmio_base + MX3_PWMPR);





		cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;

		cr = MX3_PWMCR_PRESCALER(prescale) |

			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |

			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;





		if (cpu_is_mx25())

		if (cpu_is_mx25())

			cr |= MX3_PWMCR_CLKSRC_IPG;

			cr |= MX3_PWMCR_CLKSRC_IPG;