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Commit c0d64cf9 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman
Browse files

powerpc: Use feature bit for RTC presence rather than timebase presence 



All PowerPC CPUs other than the original PPC601 have a timebase
register rather than the "real-time clock" (RTC) register that the
PPC601 (and the original POWER and POWER2 CPUs) had.  Currently
we have a CPU feature bit to indicate the presence of the timebase,
but it makes more sense to use a bit to indicate the unusual
situation rather than the common situation.  This therefore defines
a CPU_FTR_USE_RTC bit in place of the CPU_FTR_USE_TB bit, and
arranges for it to be set on PPC601 systems.

Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 7928b2cb

arch/powerpc/include/asm/cputable.h

+38 −47
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTR_ALTIVEC			ASM_CONST(0x00000008)

#define CPU_FTR_TAU			ASM_CONST(0x00000010)

#define CPU_FTR_CAN_DOZE		ASM_CONST(0x00000020)

#define CPU_FTR_USE_TB			ASM_CONST(0x00000040)

#define CPU_FTR_USE_RTC			ASM_CONST(0x00000040)

#define CPU_FTR_L2CSR			ASM_CONST(0x00000080)

#define CPU_FTR_601			ASM_CONST(0x00000100)

#define CPU_FTR_DBELL			ASM_CONST(0x00000200)
@@ -285,21 +285,19 @@ static inline void cpu_feature_keys_init(void) { } 
#endif



#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)

#define CPU_FTRS_603	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)

#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_PPC_LE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_PPC_LE)

#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_740	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750CL	(CPU_FTRS_750)
@@ -308,103 +306,96 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)

#define CPU_FTRS_750GX	(CPU_FTRS_750FX)

#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7400	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \

	    CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7448	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)

#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)

	    CPU_FTR_MAYBE_CAN_NAP)

#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON)

#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_USE_TB)

#define CPU_FTRS_8XX	(CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_440x6	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON)

#define CPU_FTRS_8XX	(CPU_FTR_NOEXECUTE)

#define CPU_FTRS_40X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_440x6	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_INDEXED_DCR)

#define CPU_FTRS_47X	(CPU_FTRS_440x6)

#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \

#define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DEBUG_LVL_EXC)

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

#define CPU_FTRS_E500MC	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)

/*

 * e5500/e6500 erratum A-006958 is a timebase bug that can use the

 * same workaround as CPU_FTR_CELL_TB_BUG.

 */

#define CPU_FTRS_E5500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

#define CPU_FTRS_E5500	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)

#define CPU_FTRS_E6500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

#define CPU_FTRS_E6500	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
@@ -412,21 +403,21 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)



/* 64-bit CPUs */

#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER4	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_STCX_CHECKS_ADDRESS)

#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PPC970	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \

	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \

	    CPU_FTR_HVMODE | CPU_FTR_DABRX)

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER5	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -434,7 +425,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \

	    CPU_FTR_DABRX)

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -443,7 +434,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | \

	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)

#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -455,7 +446,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)

#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)

#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)

#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -470,15 +461,15 @@ static inline void cpu_feature_keys_init(void) { } 
			     (~CPU_FTR_SAO))

#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9

#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_CELL	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_PPCAS_ARCH_V2)



#ifdef __powerpc64__

#ifdef CONFIG_PPC_BOOK3E

arch/powerpc/include/asm/time.h

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ struct div_result { 
/* Accessor functions for the timebase (RTC on 601) registers. */

/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */

#ifdef CONFIG_6xx

#define __USE_RTC()	(!cpu_has_feature(CPU_FTR_USE_TB))

#define __USE_RTC()	(cpu_has_feature(CPU_FTR_USE_RTC))

#else

#define __USE_RTC()	0

#endif

arch/powerpc/kernel/dt_cpu_ftrs.c

+1 −2
Original line number Diff line number Diff line
@@ -54,8 +54,7 @@ struct dt_cpu_feature { 
};



#define CPU_FTRS_BASE \

	   (CPU_FTR_USE_TB | \

	    CPU_FTR_LWSYNC | \

	   (CPU_FTR_LWSYNC | \

	    CPU_FTR_FPU_UNAVAILABLE |\

	    CPU_FTR_NODSISRALIGN |\

	    CPU_FTR_NOEXECUTE |\

arch/powerpc/kernel/vdso.c

+7 −5
Original line number Diff line number Diff line
@@ -99,26 +99,28 @@ static struct vdso_patch_def vdso_patches[] = { 
		CPU_FTR_COHERENT_ICACHE, CPU_FTR_COHERENT_ICACHE,

		"__kernel_sync_dicache", "__kernel_sync_dicache_p5"

	},

#ifdef CONFIG_PPC32

	{

		CPU_FTR_USE_TB, 0,

		CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,

		"__kernel_gettimeofday", NULL

	},

	{

		CPU_FTR_USE_TB, 0,

		CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,

		"__kernel_clock_gettime", NULL

	},

	{

		CPU_FTR_USE_TB, 0,

		CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,

		"__kernel_clock_getres", NULL

	},

	{

		CPU_FTR_USE_TB, 0,

		CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,

		"__kernel_get_tbfreq", NULL

	},

	{

		CPU_FTR_USE_TB, 0,

		CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,

		"__kernel_time", NULL

	},

#endif

};



/*