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Commit c096b1d1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "disp: msm: dsi: Fix incorrect DSI PHY timing of version 4"

parents acf75557 86162602

msm/dsi/dsi_phy_timing_calc.c

+4 −7
Original line number Original line Diff line number Diff line
@@ -474,9 +474,8 @@ static int calc_clk_post(struct dsi_phy_hw *phy, 
	t->rec_max = 255;

	t->rec_max = 255;





	/* register value */

	/* register value */

	rec_cal1 = (t->rec_max - t->rec_min);

	t->rec = DIV_ROUND_UP((((t->rec_max - t->rec_min) *

	rec_cal2 = clk_params->clk_post_buf/100;

		clk_params->clk_post_buf) + (t->rec_min * 100)), 100);

	t->rec = rec_cal1 * rec_cal2 + t->rec_min;





	rc = dsi_phy_cmn_validate_and_set(t, "clk_post");

	rc = dsi_phy_cmn_validate_and_set(t, "clk_post");

	if (rc)

	if (rc)
@@ -501,7 +500,6 @@ static int calc_clk_pre(struct dsi_phy_hw *phy, 
	s64 rec_temp1;

	s64 rec_temp1;

	s64 clk_prepare, clk_zero, clk_16;

	s64 clk_prepare, clk_zero, clk_16;

	u32 input1;

	u32 input1;

	s64 rec_cal1, rec_cal2;





	/* mipi min */

	/* mipi min */

	t->mipi_min = cal_clk_pulse_time(8, 0, clk_params->bitclk_mbps);

	t->mipi_min = cal_clk_pulse_time(8, 0, clk_params->bitclk_mbps);
@@ -526,9 +524,8 @@ static int calc_clk_pre(struct dsi_phy_hw *phy, 
	t->rec_max = 255;

	t->rec_max = 255;





	/* register value */

	/* register value */

	rec_cal1 = (t->rec_max - t->rec_min);

	t->rec =DIV_ROUND_UP((((t->rec_max - t->rec_min) *

	rec_cal2 = clk_params->clk_pre_buf/100;

		125) + (t->rec_min * 100 * 100)), 100 * 100);

	t->rec = rec_cal1 * rec_cal2 + t->rec_min;





	rc = dsi_phy_cmn_validate_and_set(t, "clk_pre");

	rc = dsi_phy_cmn_validate_and_set(t, "clk_pre");

	if (rc)

	if (rc)

msm/dsi/dsi_phy_timing_v4_0.c

+15 −12
Original line number Original line Diff line number Diff line
@@ -9,21 +9,24 @@ 
void dsi_phy_hw_v4_0_get_default_phy_params(

void dsi_phy_hw_v4_0_get_default_phy_params(

		struct phy_clk_params *params)

		struct phy_clk_params *params)

{

{

	params->clk_prep_buf = 0;

	params->clk_prep_buf = 50;

	params->clk_zero_buf = 0;

	params->clk_zero_buf = 2;

	params->clk_trail_buf = 0;

	params->clk_trail_buf = 30;

	params->hs_prep_buf = 0;

	params->hs_prep_buf = 50;

	params->hs_zero_buf = 0;

	params->hs_zero_buf = 10;

	params->hs_trail_buf = 0;

	params->hs_trail_buf = 30;

	params->hs_rqst_buf = 0;

	params->hs_rqst_buf = 0;

	params->hs_exit_buf = 0;

	params->hs_exit_buf = 10;

	/* 1.25 is used in code for precision */

	params->clk_pre_buf = 1;

	params->clk_post_buf = 5;

}

}





int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult)

int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult)

{

{

	s64 rec_temp2, rec_temp3;

	s64 rec_temp2, rec_temp3;





	rec_temp2 = (rec_temp1 - mult);

	rec_temp2 = rec_temp1;

	rec_temp3 = roundup(div_s64(rec_temp2, 8), mult);

	rec_temp3 = roundup(div_s64(rec_temp2, 8), mult);

	return (div_s64(rec_temp3, mult) - 1);

	return (div_s64(rec_temp3, mult) - 1);

}

}
@@ -33,7 +36,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_min(s64 temp_mul, 
{

{

	s64 rec_temp1, rec_temp2, rec_temp3;

	s64 rec_temp1, rec_temp2, rec_temp3;





	rec_temp1 = temp_mul + frac;

	rec_temp1 = temp_mul;

	rec_temp2 = div_s64(rec_temp1, 8);

	rec_temp2 = div_s64(rec_temp1, 8);

	rec_temp3 = roundup(rec_temp2, mult);

	rec_temp3 = roundup(rec_temp2, mult);

	return (div_s64(rec_temp3, mult) - 1);

	return (div_s64(rec_temp3, mult) - 1);
@@ -84,11 +87,11 @@ void dsi_phy_hw_v4_0_update_timing_params( 
	timing->lane_v4[6] = desc->hs_prepare.reg_value;

	timing->lane_v4[6] = desc->hs_prepare.reg_value;

	timing->lane_v4[7] = desc->hs_trail.reg_value;

	timing->lane_v4[7] = desc->hs_trail.reg_value;

	timing->lane_v4[8] = desc->hs_rqst.reg_value;

	timing->lane_v4[8] = desc->hs_rqst.reg_value;

	timing->lane_v4[9] = 0x03;

	timing->lane_v4[9] = 0x02;

	timing->lane_v4[10] = 0x04;

	timing->lane_v4[10] = 0x04;

	timing->lane_v4[11] = 0x00;

	timing->lane_v4[11] = 0x00;

	timing->lane_v4[12] = 0x00;

	timing->lane_v4[12] = desc->clk_pre.reg_value;

	timing->lane_v4[13] = 0x00;

	timing->lane_v4[13] = desc->clk_post.reg_value;





	pr_debug("[%d %d %d %d]\n", timing->lane_v4[0],

	pr_debug("[%d %d %d %d]\n", timing->lane_v4[0],

		timing->lane_v4[1], timing->lane_v4[2], timing->lane_v4[3]);

		timing->lane_v4[1], timing->lane_v4[2], timing->lane_v4[3]);