Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c03af1ae authored by Jayamohan Kallickal's avatar Jayamohan Kallickal Committed by James Bottomley
Browse files

[SCSI] be2iscsi: Alloc only one EQ if intr mode 



This patch ensures that we alloc only one EQ
if we are if we are not in msix mode

Signed-off-by: default avatarJayamohan Kallickal <jayamohank@serverengines.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
parent ed58ea2a

drivers/scsi/be2iscsi/be_main.c

+9 −5
Original line number Original line Diff line number Diff line
@@ -3190,14 +3190,18 @@ static unsigned char hwi_enable_intr(struct beiscsi_hba *phba) 
		reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;

		reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;

		SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p \n", reg, addr);

		SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p \n", reg, addr);

		iowrite32(reg, addr);

		iowrite32(reg, addr);

		if (!phba->msix_enabled) {

			eq = &phwi_context->be_eq[0].q;

			SE_DEBUG(DBG_LVL_8, "eq->id=%d \n", eq->id);

			hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);

		} else {

			for (i = 0; i <= phba->num_cpus; i++) {

			for (i = 0; i <= phba->num_cpus; i++) {

				eq = &phwi_context->be_eq[i].q;

				eq = &phwi_context->be_eq[i].q;

				SE_DEBUG(DBG_LVL_8, "eq->id=%d \n", eq->id);

				SE_DEBUG(DBG_LVL_8, "eq->id=%d \n", eq->id);

				hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);

				hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);

			}

			}

	} else

		}

		shost_printk(KERN_WARNING, phba->shost,

	}

			     "In hwi_enable_intr, Not Enabled \n");

	return true;

	return true;

}

}